Hao Yu
ABSTRACT
We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vector potential equivalent circuit) model, which not only enables the passive sparsification but also gives correct low-frequency response, whereas the recent circuit reduction intrinsically has inaccurate value and low-frequency response due to nodal-susceptance formulation. Applying hierarchical circuit-reduction enhanced by multi-point expansions, we can obtain an accurate high-order impedance function to capture the high-frequency response. The impedance function is further enforced passivity by convex programming, and realized by a Foster's synthesis. Experiments show that our method is as accurate as PRIMA in high frequency range, but leads to a realized circuit model with up to 10X times less complexity and up to 8X smaller simulation time. In addition, under the same reduction ratio, its error margin is less than that for the time-constant based reduction in both time-domain and frequency-domain simulations.
- A. E. Ruehli, "Equivalent circuits models for three dimensional multiconductor systems," IEEE T-MTT, pp. 216-220, 1974.Google Scholar
- K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE T-CAD, pp. 1447-1459, 1991.Google Scholar
- M. Kamon, M. Tsuk, and J. White, "FastHenry: a multipole-accelerated 3D inductance extraction program," IEEE T-MTT, pp. 1750-1758, 1994.Google Scholar
- Z. He, M. Celik, and L. Pillegi, "SPIE: Sparse partial inductance extraction," in DAC, pp. 137-140, 1997. Google ScholarDigital Library
- A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in ICCAD, pp. 150-155, 2000. Google ScholarDigital Library
- H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion," in DAC, pp. 781-723, 2003. Google ScholarDigital Library
- A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE T-CAD, pp. 645-654, 1998. Google ScholarDigital Library
- L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE T-CAD, pp. 352-366, 1990.Google Scholar
- C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, "Realizable rlck circuit crunching," in DAC, pp. 226-231, 2003. Google ScholarDigital Library
- Z. Qin and C. Cheng, "Realizable parasitic reduction using generalized transformation," in DAC, pp. 220-225, 2003. Google ScholarDigital Library
- G. C. Temes and J. Lapatra, Introduction to circuit synthesis and design. Mcgraw-Hilll Book Company, 1977.Google Scholar
- K. S. Kundert, The designer's guide to SPICE and SPECTRE. Kluwer Academic Publishers, 1995. Google ScholarDigital Library
- S. X. D. Tan, "A general s-domain hierarchical network reduction algorithm," ICCAD, pp. 650-657, 2003. Google ScholarDigital Library
- E. Chiprout and M. Nakhla, "Analysis of interconnect networks using complex frequency hopping (CFH)," IEEE T-CAD, pp. 186-200, 1995. Google ScholarDigital Library
- T. Mangold and P. Russer, "Full-wave modeling and automatic equivalent-circuit generation of millimeter-wave planar and multilayer structures," IEEE T-MTT, pp. 851-858, 1999.Google Scholar
- M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," in DATE, pp. 430-436, 2001. Google ScholarDigital Library
- B. D. O. Anderson, "A system theory criterion for positive real matrices," SIAM J. Contr. , pp. 171 - 182, 1967.Google Scholar
- C. P. Coelho, J. Philips, and L. M. Silverira, "A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data," IEEE T-CAD, pp. 293-301, 2004. Google ScholarDigital Library
- M. Celik, L. Pileggi, and A. Odabasioglu, IC interconnect analysis. Kluwer Academic Publishers, 2002.Google Scholar
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