Article

Wave-pipelined on-chip global interconnect

Authors:

Charlie Chung-Ping ChenAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 127 - 132

https://doi.org/10.1145/1120725.1120788

Published: 18 January 2005 Publication History

Abstract

A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal propagation path and a single type of 1-input gate(inverter), a wave-pipelined interconnect will have less stringent timing constraints than a wave-pipelined combinational logic block. A phase-lock loop based clock and data recovery unit architecture, adopted from off-chip high speed digital serial link, is designed for on-chip application so as to minimize power and area cost. Preliminary Monte Carlo simulation indicated that the wave-pipelined global interconnect architecture potentially can offer 18% higher throughput than a flip-flop pipelined global interconnect architecture at about the same level of reliability. While delivering data through long interconnect at the same bit rate, the wave-pipelined architecture consumes less power and requires less chip real estate.

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Cited By

Pasricha SDutt N(2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00006-2
Sylvester DSrivastava A(2007)Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOSProceedings of the IEEE10.1109/JPROC.2006.88937095:3(507-529)Online publication date: Mar-2007
https://doi.org/10.1109/JPROC.2006.889370
Haikun Zhu Rui Shi Chung-Kuan Cheng Hongyu Chen (2007)Approaching Speed-of-light Distortionless Communication for On-chip InterconnectProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358066(684-689)Online publication date: 23-Jan-2007
https://dl.acm.org/doi/10.1109/ASPDAC.2007.358066
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Wave-pipelined on-chip global interconnect
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cover image ACM Conferences

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE SSCS Shanghai Chapter
IEEE Beijing Section
SIGDA: ACM Special Interest Group on Design Automation
Fudan University
IEEE CAS
Chinese Institute of Electronics
Shanghai IC Industry Association

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Pasricha SDutt N(2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00006-2
Sylvester DSrivastava A(2007)Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOSProceedings of the IEEE10.1109/JPROC.2006.88937095:3(507-529)Online publication date: Mar-2007
https://doi.org/10.1109/JPROC.2006.889370
Haikun Zhu Rui Shi Chung-Kuan Cheng Hongyu Chen (2007)Approaching Speed-of-light Distortionless Communication for On-chip InterconnectProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358066(684-689)Online publication date: 23-Jan-2007
https://dl.acm.org/doi/10.1109/ASPDAC.2007.358066
Singhal RChoi GMahapatra RHassoun S(2006)Information theoretic approach to address delay and reliability in long on-chip interconnectsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233563(310-314)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233563
Hon MHirose F(2006)Spec-based flip-flop and latch repeater planningProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118380(326-331)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118380
Xu JChowdhury M(2006)Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining2006 13th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2006.379621(1061-1064)Online publication date: Dec-2006
https://doi.org/10.1109/ICECS.2006.379621
Singhal RChoi GMahapatra R(2006)Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320051(310-314)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320051
Xu JChowdhury M(2006)Latch Based Interconnect Pipelining For High Speed Integrated Circuits2006 IEEE International Conference on Electro/Information Technology10.1109/EIT.2006.252152(295-300)Online publication date: May-2006
https://doi.org/10.1109/EIT.2006.252152
Man Chung Hon (2006)Spec-based flip-flop and latch repeater planningAsia and South Pacific Conference on Design Automation, 2006.10.1109/ASPDAC.2006.1594703(326-331)Online publication date: 2006
https://doi.org/10.1109/ASPDAC.2006.1594703
Seth VZhao MHu J(2004)Exploiting level sensitive latches in wire pipeliningProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382587(283-290)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382587

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