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Propagation delay fault: a new fault model to test delay faults

Published: 18 January 2005 Publication History

Abstract

A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model.

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  1. Propagation delay fault: a new fault model to test delay faults

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    cover image ACM Conferences
    ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
    January 2005
    1495 pages
    ISBN:0780387376
    DOI:10.1145/1120725
    • General Chair:
    • Ting-Ao Tang
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 January 2005

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    • (2020)Non-Masking Non-Robust Tests for Path Delay Faults2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107556(1-6)Online publication date: Apr-2020
    • (2017)Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites2017 IEEE 26th Asian Test Symposium (ATS)10.1109/ATS.2017.19(34-39)Online publication date: Nov-2017
    • (2011)Delay Faults TestingDesign and Test Technology for Dependable Systems-on-Chip10.4018/978-1-60960-212-3.ch017(377-394)Online publication date: 2011
    • (2010)SfW method: Delay test generation for simple chain wrapper architectureNORCHIP 201010.1109/NORCHIP.2010.5669457(1-4)Online publication date: Nov-2010
    • (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
    • (2006)Recognition of Sensitized Longest Paths in Transition Delay Test2006 IEEE International Test Conference10.1109/TEST.2006.297622(1-6)Online publication date: Oct-2006
    • (2006)Delay Fault Diagnosis for Non-Robust TestProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.45(463-472)Online publication date: 27-Mar-2006
    • (2006)State-of-art of delay testing2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design10.1109/CAIDCD.2006.329360(1-4)Online publication date: Nov-2006

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