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Oscillation ring based interconnect test scheme for SOC

Published: 18 January 2005 Publication History

Abstract

We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.

References

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Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2003.
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M. Kaneko and K. Sakaguchi, "Oscillation Fault Diagnosis for Analog Circuits Based on Boundary Search with Perturbation Model," in Proc. IEEE ISCAS, pp93--96, 1994.
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K. Arabi, B. Kaminska, "Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits," in Proc. Int'l Test Conf., pp. 786--795, 1997.
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W. C. Wu, C. L. Lee, M. S. Wu, J. E. Chen, and M. Abadir, "Oscillation Ring Delay Test for High Performance Microprocessor", JETTA, pp. 147--155, 2000.
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C. W. Yau and N. Jarwala, "A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects," in Proc. Int'l Test Conf., pp. 71--77, 1989.
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F. DaSilva, Y. Zorian, L. Whetsel, K. Arabi, R. Kapur, "Overview of the ieee P1500 standard," in Proc. Int'l Test Conf., pp. 988--997, 2003.
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IEEE P1500, http://grouper.ieee.org/groups/1500/.
[9]
K. S.-M. Li, C.-L. Lee, C. Su, J. E. Chen, "A Unified Detection Scheme and its Fault Effects of Interconnection Bus Crosstalk Faults in Deep Submicron VLSI" to be presented in Asia Test Sym., Nov. 2004.

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  • (2018)Reconfigurable RO-Path Delay SensorIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2018.279850365:12(2027-2031)Online publication date: Dec-2018
  • (2016)Testing of small delay faults in a clock network2016 21th IEEE European Test Symposium (ETS)10.1109/ETS.2016.7519291(1-6)Online publication date: May-2016
  • (2016)Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.67(80-85)Online publication date: Nov-2016
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  1. Oscillation ring based interconnect test scheme for SOC

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    cover image ACM Conferences
    ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
    January 2005
    1495 pages
    ISBN:0780387376
    DOI:10.1145/1120725
    • General Chair:
    • Ting-Ao Tang
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 January 2005

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    Cited By

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    • (2018)Reconfigurable RO-Path Delay SensorIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2018.279850365:12(2027-2031)Online publication date: Dec-2018
    • (2016)Testing of small delay faults in a clock network2016 21th IEEE European Test Symposium (ETS)10.1109/ETS.2016.7519291(1-6)Online publication date: May-2016
    • (2016)Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.67(80-85)Online publication date: Nov-2016
    • (2015)Feedback-bus oscillation ringProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757027(924-927)Online publication date: 9-Mar-2015
    • (2014)Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229058933:3(476-488)Online publication date: 1-Mar-2014
    • (2013)Oscillation and Transition Tests for Synchronous Sequential CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223065421:12(2338-2343)Online publication date: 1-Dec-2013
    • (2013)In-situ method for TSV delay testing and characterization using input sensitivity analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218754321:3(443-453)Online publication date: 1-Mar-2013
    • (2013)Delay testing and characterization of post-bond interposer wires in 2.5-D ICs2013 IEEE International Test Conference (ITC)10.1109/TEST.2013.6651906(1-8)Online publication date: Sep-2013
    • (2013)Process monitoring through wafer-level spatial variation decomposition2013 IEEE International Test Conference (ITC)10.1109/TEST.2013.6651901(1-10)Online publication date: Sep-2013
    • (2013)Oscillation-Based Prebond TSV TestIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225962632:9(1440-1444)Online publication date: 1-Sep-2013
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