Article

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation

Authors:

Charlie Chung-Ping ChenAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 381 - 386

https://doi.org/10.1145/1120725.1120881

Published: 18 January 2005 Publication History

Abstract

Simultaneous gate-sizing with multiple V_t assignment for delay and power optimization is a complicated task in modern custom designs. In this work, we make the key contribution of a novel gate-sizing and multi-V_t assignment technique based on generalized Lagrangian Relaxation. Experimental results show that our technique exhibits linear runtime and memory usage, and can effectively tune circuits with over 15,000 variables and 8,000 constraints in under 8 minutes (250x faster than state-of-the-art optimization solvers).

References

[1]

A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah, "Jiffytune: circuit optimization using time-domain sensitivities," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 17, no. 12, pp. 1292--1309, December 1998.

Digital Library

[2]

C. P. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 18, no. 7, pp. 1014--1025, July 1999.

Digital Library

[3]

Y. Jiang, S. Sepatnekar, C. Bamji, and J. Kim, "Combined transistor sizing with buffer insertion for timing optimization."

[4]

M. Borah, R. M. Owens, and M. J. Irwin, "Transistor sizing for low power cmos circuits," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 15, no. 6, pp. 665--671, June 1996.

Digital Library

[5]

M. Hirabayashi, K. Nose, and T. Sakurai, "Design methodology and optimization strategy for dual-vth scheme using commercially available tools," in Proc. of the International symposium on Low power electronics and design, 2001, pp. 283--286.

Digital Library

[6]

N. Tripathi, A. Bhosle, D. Samanta, and A. Pal, "Optimal assignment of high threshold voltage for synthesizing dual threshold cmos circuits," in VLSI Design, India, 2001, pp. 227--232.

Digital Library

[7]

T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar, "Total power optimization by simultaneous dual-vt allocation and device sizing in high performance microprocessors," in IEEE/ACM DAC, 2002, pp. 486--491.

Digital Library

[8]

A. Srivastava, D. Silvester, and D. Blaauw, "Concurrent sizing, vdd, and v/sub th/ assignment for low power design," in Design, Automation, and Test in Europe, 2004, pp. 718--719.

Digital Library

[9]

M. S. Bazaraa, H. D. Sherali, and C. M. Shetty, Nonlinear Programming: Theory and Algorithms, 2nd ed. New York: Wiley, 1997.

[10]

K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar, "A new class of convex functions for delay modeling and their application to the transistor sizing problem," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 19, no. 7, pp. 779--788, July 2000.

Digital Library

[11]

P. E. Gill, W. Murray, and M. A. Saunders, "Snopt: An sqp algorithm for large-scale constrained optimization," Department of Mathematics, University of California, San Diego, La Jolla, CA, Numerical Analysis Report 97-2, 1997.

[12]

Lawrence, C., Zhou, J. L., Tits, and A. L., "User's guide for cfsqp version 2.4: A c code for solving (large scale) constrained nonlinear (minmax) optimization problems, generating iterates satisfying all inequality constraints," Institute for Systems Research, University of Maryland, College Park, MD, Tech. Rep. TR-94-16rl, 1996.

[13]

J. Nocedal and S. J. Wright, Numerical Optimization. Heidelberg, Berlin, New York: Springer Verlag, 1999.

[14]

H. Tennakoon and C. Sechen, "Gate sizing using lagrangian relaxation combined with a fast gradient-based pre-processing step," in ICCAD, 2002, pp. 395--402.

Digital Library

[15]

A. R. Conn, N. Gould, and P. L. Toint, "Global convergence of a class of trust region algorithms for optimization with simple bounds," SIAM J Numerical Analysis, vol. 25, pp. 433--460, 1988.

Digital Library

[16]

R. H. Byrd, P. Lu, J. Nocedal, and C. Zhu, "A limited memory algorithm for bound constrained optimization," Northwestern University EECS," Technical Report NAM-08, 1994.

[17]

S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhary, R. Panda, and D. Blauuw, "Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing," in IEEE/ACM DAC, 1999, pp. 436--441.

Digital Library

[18]

P. Pant, R. K. Roy, and A. Chatterjee, "Dual-threshold voltage assignment with transistor sizing for low power cmos circuits," IEEE Transactions on VLSI Systems, vol. 9, no. 2, pp. 390--394, April 2001.

Digital Library

[19]

M. Ketkar and S. Sapatnekar, "Parameter variations and impacts on circuits and microarchitecture," in IEEE Conference on Computer-Aided Design, 2002, pp. 375--378.

[20]

D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer, "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization," in International Symposium on Low-Power Electronics and Design, 2003, pp. 158--163.

Digital Library

Cited By

Cheng CHoltz CKahng ALin BMallappa U(2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3577019
Mallappa UCheng C(2021)GRA-LPOProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431574(697-702)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431574
Yella ASechen C(2017) Improved lagrangian relaxation-based gate size and V T assignment for very large circuits 2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2017.7899169(1-4)Online publication date: Feb-2017
https://doi.org/10.1109/PRIME-LA.2017.7899169
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Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
1. Theory of computation
  1. Design and analysis of algorithms

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cover image ACM Conferences

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE SSCS Shanghai Chapter
IEEE Beijing Section
SIGDA: ACM Special Interest Group on Design Automation
Fudan University
IEEE CAS
Chinese Institute of Electronics
Shanghai IC Industry Association

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Cheng CHoltz CKahng ALin BMallappa U(2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3577019
Mallappa UCheng C(2021)GRA-LPOProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431574(697-702)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431574
Yella ASechen C(2017) Improved lagrangian relaxation-based gate size and V T assignment for very large circuits 2017 1st Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)10.1109/PRIME-LA.2017.7899169(1-4)Online publication date: Feb-2017
https://doi.org/10.1109/PRIME-LA.2017.7899169
Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Roy SLiu DUm JPan D(2015)OSFAProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744885(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744885
Reimann TSze CReis R(2015)Gate sizing and threshold voltage assignment for high performance microprocessor designsThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059007(214-219)Online publication date: Jan-2015
https://doi.org/10.1109/ASPDAC.2015.7059007
Livramento VGuth CGüntzel JJohann M(2014)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian RelaxationACM Transactions on Design Automation of Electronic Systems10.1145/264795619:4(1-25)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647956
Flach GReimann TPosser GJohann MReis R(2014)Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian RelaxationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230584733:4(546-557)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TCAD.2014.2305847
Ozdal MAmin CAyupov ABurns SWilke GZhuo CKoh CSze C(2013)An improved benchmark suite for the ISPD-2013 discrete cell sizing contestProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451959(168-170)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451959
Flach GReimann TPosser GJohann MReis R(2013)Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2013.6654627(84-89)Online publication date: Aug-2013
https://doi.org/10.1109/ISVLSI.2013.6654627
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