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SAGA: synthesis technique for guaranteed throughput NoC architectures

Published: 18 January 2005 Publication History

Abstract

We present SAGA, a novel genetic algorithm (GA) based technique for synthesis of custom NoC architectures that support guaranteed throughput traffic. The technique accepts as input a communication trace graph, amount of data, period, and deadline for each trace, interconnection network architecture elements, and generates a custom NoC topology, and routing and schedule of the communication traces on the architecture. SAGA minimizes both the energy consumption and area of the design by solving a multi-objective optimization problem. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions. SAGA is able to generate solutions that are as good as the optimal solutions produced by the MILP formulation. Whereas the MILP formulation run time rises exponentially for even moderately sized graphs, SAGA generates solutions for large graphs in reasonable time.

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
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Publication History

Published: 18 January 2005

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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  • (2015)Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft coresJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2014.11.00161:1(1-11)Online publication date: 1-Jan-2015
  • (2013)CusNoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219568821:4(692-705)Online publication date: 1-Apr-2013
  • (2013)Application-Specific Network-on-Chip synthesis with flexible router PlacementJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.05.01359:7(361-371)Online publication date: 1-Aug-2013
  • (2007)System-Level Design of Network-on-Chip ArchitecturesDesigning Embedded Processors10.1007/978-1-4020-5869-1_18(391-422)Online publication date: 2007
  • (2006)A low complexity heuristic for design of custom network-on-chip architecturesProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131521(130-135)Online publication date: 6-Mar-2006
  • (2006)A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip ArchitecturesProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.13(352-357)Online publication date: 27-Mar-2006

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