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Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Authors:

Jeng-Liang Tsai,

Charlie Chung-Ping ChenAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1168 - 1171

https://doi.org/10.1145/1120725.1120932

Published: 18 January 2005 Publication History

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Abstract

Zero-skew clock-tree with minimum clock-delay is preferable due to its low unintentional and process-variation induced skews. We propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout the full zero-skew design-space by considering simultaneous buffer-insertion, buffer-sizing, and wire-sizing. For an industrial clock-tree with 3101 sink nodes, our algorithm achieves up to 45X clock-delay improvement and up to 23% power reduction compared with its initial routing.

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Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Lin MChih-Cheng Hsu Yu-Chuan Chen (2015)Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237698834:2(280-292)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TCAD.2014.2376988
Narasimhan ASridhar R(2010)Variability aware low-power delay optimal buffer insertion for global interconnectsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.207379057:12(3055-3063)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TCSI.2010.2073790

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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 18 January 2005

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ASPDAC05

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SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Lin MChih-Cheng Hsu Yu-Chuan Chen (2015)Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237698834:2(280-292)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TCAD.2014.2376988
Narasimhan ASridhar R(2010)Variability aware low-power delay optimal buffer insertion for global interconnectsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2010.207379057:12(3055-3063)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/TCSI.2010.2073790

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Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

Type-matching clock tree for zero skew clock gating

Zero-Skew Driven Buffered RLC Clock Tree Construction

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