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Simultaneous floorplanning and resource binding: a probabilistic approach

Published: 18 January 2005 Publication History

Abstract

In this work we present a probabilistic approach to simultaneous floorplanning and resource binding for low power. Traditional approaches iteratively perform floorplanning and resource binding while using crude deterministic wire-length estimates like bounding box (since we do not have routing information for inter module inter-connect). Non-availability of accurate wire-length results in suboptimal design and failure of timing closure. In this work we model the wire-lengths as probability distributions and propose a novel probabilistic optimization methodology. Experimental results using state of the art commercial and academic tools were conducted. The novelty in this work is in the higher chance of ending with a feasible design that is synthesizable without losing in overall power (interconnect + module + register). Experimental results show that on-average the number of unsynthesized modules after routing for Mediabench benchmarks were 2 in the conventional case, while on average our probabilistic approach had all modules synthesized after routing.

References

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A. Davoodi and A. Srivastava. "Voltage Scheduling Under Unpredictabilities: A Risk Management Paradigm". In ACM/IEEE Int'l Symposium on Low Power Electronics and Design, August 2003.
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A. Davoodi, V. Khandelwal, A. Srivastava. "Empirical Models for Net-Length Probability Distribution and Applications". In IEEE Transactions on Very Large Scale Integration Systems, October 2004.
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A. Srivastava and Majid Sarrafzadeh. "Predictability: Definition, Analysis and Optimization". In Procs of International Conference on Computer Aided Design, Nov. 2002.
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C. Visweswariah. "Death, Taxes and Failing Chips". In Proc. of Design Automation Conference, June 2003.
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J. M. Chang and M. Pedram. "Low Power Register Allocation and Binding". In Proc. Design Automation Conference, pages 29--35, June 1995.
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A. Srivastava E. Kursun and M. Sarrafzadeh. "Predictability Driven Binding: Methodologies and Tradeoffs". In Journal of Circuits, Systems and Computers, Special Issue on Low Power IC Designs, 2002.
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Lin Zhong and Niraj K. Jha. "Interconnect-aware high-level synthesis for low power". In Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pages 110--117, 2002.
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Min Xu, Fadi J. Kurdahi. "Layout-driven RTL binding techniques for high-level synthesis using accurate estimators". In ACM Transactions on Design Automation of Electronic Systems (TODAES), pages 312--343, Oct. 1997.
[9]
R. Kastner, E. Bozorgzadeh M. Sarrafzadeh. "Predictable Routing". In Proc. of IEEE International Conference on Computer-Aided Design, Nov. 2000.
[10]
S. Adya, I. Markov. "Fixed-outline Floorplanning Through Better Local Search". In Proc. of ACM/IEEE International Conference Computer Design, pages 321--334, 2001.

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
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Published: 18 January 2005

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