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Studying interactions between prefetching and cache line turnoff

Published:18 January 2005Publication History

ABSTRACT

While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance-oriented techniques influence energy behavior of the cache, and the energy-oriented techniques usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper studies this interaction and illustrates how performance and energy optimizations affect each other. We also point out several potential optimizations that could be based on this study.

References

  1. "Spec cpu2000 benchmark. http://www.spec.org/".Google ScholarGoogle Scholar
  2. D. C. Burger and T. M. Austin, "The SimpleScalar toolset, version 2.0," Tech. Rep. 1342, Dept. of Computer Science, UW, June 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. K. K. Chan, "Design of the HP PA 7200 cpu", Hewlett-packard J., vol. 47, no. 1, pp. 25--33.Google ScholarGoogle Scholar
  4. M. Kamble and K. Ghose, "Energy efficiency of VLSI caches: a comparative study," in Proceedings of the International Conference on VLSI Design, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: exploiting general behavior to reduce cache leakage power," in Proceedings of the 28th Annual International Symposium on Computer Architecture, pp. 240--251, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. L. Li, I. Kadayif, Y. F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam, "Leakage energy management in cache hierarchies," in the 11th International Conference on Parallel Architectures and Compilation Techniques, pp. 131--140, September 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. J. Montenaro et al., "160 mHz 32b 0.5w CMOS RISC Microprocessor," in Proceedings of the International Solid State Circuits Conference, 1996.Google ScholarGoogle Scholar
  8. P. Shivakumar and N. P. Jouppi, "Cacti 3.0: an integrated cache timing, power, and area model," Technical Report, Digital Equipment Corporation, 1990.Google ScholarGoogle Scholar
  9. A. J. Smith, "Cache memories", ACM Computing Survey, vol, 14, no. 3, September 1982. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. S. P. Vanderwiel and D. J. Lilja, "Data prefetch mechanisms", ACM Computing Surveys, vol. 32, no. 2, June 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  1. Studying interactions between prefetching and cache line turnoff

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        • Published in

          cover image ACM Conferences
          ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
          January 2005
          1495 pages
          ISBN:0780387376
          DOI:10.1145/1120725
          • General Chair:
          • Ting-Ao Tang

          Copyright © 2005 ACM

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          New York, NY, United States

          Publication History

          • Published: 18 January 2005

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