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An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Authors:

Lingfeng Li,

Satoshi Goto,

Takeshi IkenagaAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 623 - 626

https://doi.org/10.1145/1120725.1120978

Published: 18 January 2005 Publication History

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Abstract

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35μm technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

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Khraisha RLee J(2012)A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial ReconfigurationJournal of Signal Processing Systems10.1007/s11265-011-0584-z66:3(225-234)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1007/s11265-011-0584-z
Lai YChen LChiou W(2010)A memory interleaving and interlacing architecture for deblocking filter in H.264/AVCIEEE Transactions on Consumer Electronics10.1109/TCE.2010.568117356:4(2812-2818)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCE.2010.5681173
Liu TYang ECheng RFu Y(2010)CUDA-based H.264/AVC deblocking filtering2010 International Conference on Audio, Language and Image Processing10.1109/ICALIP.2010.5684535(1547-1551)Online publication date: Nov-2010
https://doi.org/10.1109/ICALIP.2010.5684535
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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Khraisha RLee J(2012)A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial ReconfigurationJournal of Signal Processing Systems10.1007/s11265-011-0584-z66:3(225-234)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1007/s11265-011-0584-z
Lai YChen LChiou W(2010)A memory interleaving and interlacing architecture for deblocking filter in H.264/AVCIEEE Transactions on Consumer Electronics10.1109/TCE.2010.568117356:4(2812-2818)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCE.2010.5681173
Liu TYang ECheng RFu Y(2010)CUDA-based H.264/AVC deblocking filtering2010 International Conference on Audio, Language and Image Processing10.1109/ICALIP.2010.5684535(1547-1551)Online publication date: Nov-2010
https://doi.org/10.1109/ICALIP.2010.5684535
Kwon YEum N(2010)Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processorMicroprocessors & Microsystems10.1016/j.micpro.2009.10.00234:1(1-13)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1016/j.micpro.2009.10.002
Lin YLin Y(2009)A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoderIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200845617:6(838-843)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008456
Gligor MFournel NPétrot FColas-Bigey FFouilliart ATeninge PCoppola M(2009)Practical design space exploration of an h264 decoder for handheld devices using a virtual platformProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_25(206-215)Online publication date: 9-Sep-2009
https://dl.acm.org/doi/10.1007/978-3-642-11802-9_25
Dang P(2008)High performance architecture of an application specific processor for the H.264 deblocking filterIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515843.151585016:10(1321-1334)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.5555/1515843.1515850
Peng JYan XLi DChen L(2008)A parallel memory architecture for video codingJournal of Zhejiang University-SCIENCE A10.1631/jzus.A08200529:12(1644-1655)Online publication date: 1-Dec-2008
https://doi.org/10.1631/jzus.A0820052
Chih-Hung Li Wen-Hsiao Peng Tihao Chiang (2008)Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling2008 IEEE International Conference on Multimedia and Expo10.1109/ICME.2008.4607619(1053-1056)Online publication date: Jun-2008
https://doi.org/10.1109/ICME.2008.4607619
Aho EVanne JHämäläinen T(2008)Configurable data memory for multimedia processingJournal of Signal Processing Systems10.1007/s11265-007-0126-x50:2(231-249)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1007/s11265-007-0126-x
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A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC

General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

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