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An FPGA implementation of low-density parity-check code decoder with multi-rate capability

Published: 18 January 2005 Publication History

Abstract

With superior error correction capability, low-density parity-check (LDPC) has initiated wide scale interests in wireless telecommunication fields. In the past, various structures of single code rate LDPC decoders have been implemented for different applications. However, in order to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate in both high and low code rates are desired. In this paper, a new multi-rate LDPC decoder architecture is presented and implemented in a Xilinx FPGA device. Through selection pins, three operating modes with the irregular 1/2 rate, regular 5/8 rate and regular 7/8 rate are supported. The measurement results show LDPC decoder can achieve BER below 10-5 at SNR of 1.4dB in the most critical case with the irregular 1/2 mode.

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A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder", IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404--412, March 2002.
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Cited By

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  • (2018)Structure and flexibility of LDPC codesResource Efficient LDPC Decoders10.1016/B978-0-12-811255-7.00003-4(11-28)Online publication date: 2018
  • (2011)A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decodersProceedings of the 2011 IEEE International Conference on Multimedia and Expo10.1109/ICME.2011.6011832(1-7)Online publication date: 11-Jul-2011
  • (2010)Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders2010 13th International Conference on Computer and Information Technology (ICCIT)10.1109/ICCITECHN.2010.5723842(131-136)Online publication date: Dec-2010
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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 January 2005

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Cited By

View all
  • (2018)Structure and flexibility of LDPC codesResource Efficient LDPC Decoders10.1016/B978-0-12-811255-7.00003-4(11-28)Online publication date: 2018
  • (2011)A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decodersProceedings of the 2011 IEEE International Conference on Multimedia and Expo10.1109/ICME.2011.6011832(1-7)Online publication date: 11-Jul-2011
  • (2010)Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders2010 13th International Conference on Computer and Information Technology (ICCIT)10.1109/ICCITECHN.2010.5723842(131-136)Online publication date: Dec-2010
  • (2009)Memory efficient multi-rate regular LDPC decoder for CMMBIEEE Transactions on Consumer Electronics10.1109/TCE.2009.537374455:4(1866-1874)Online publication date: 1-Nov-2009
  • (2007)VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes2007 2nd International Symposium on Wireless Pervasive Computing10.1109/ISWPC.2007.342667Online publication date: Feb-2007
  • (2007)VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax2007 IEEE International Conference on Communications10.1109/ICC.2007.750(4542-4547)Online publication date: Jun-2007
  • (2006)A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311328(1-6)Online publication date: Aug-2006
  • (2006)Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation2006 Fortieth Asilomar Conference on Signals, Systems and Computers10.1109/ACSSC.2006.354944(1192-1199)Online publication date: Oct-2006

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