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Adiabatic CMOS gate and adiabatic circuit design for low-power applications

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Guoqiang HangAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 803 - 808

https://doi.org/10.1145/1120725.1121022

Published: 18 January 2005 Publication History

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Abstract

The methodology for designing adiabatic circuits employing two-phase power clock, is investigated. First, algebraic expressions for and properties of power-clocked signals are discussed. Then the design of adiabatic gates based on AC power supply and CMOS transmission gates is analyzed. On this basis, basic rules for the design of adiabatic circuits are proposed, and a design example of an adiabatic full adder is demonstrated. SPICE simulations using a trapezoidal power-clock demonstrate that the designed adiabatic circuits have a correct logic function and ultra low-power characteristics.

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Wisetphanichkij SDejhan K(2009)The Combinational and Sequential Adiabatic Circuit Design and Its ApplicationsCircuits, Systems, and Signal Processing10.1007/s00034-009-9096-528:4(523-534)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1007/s00034-009-9096-5
Wang PYu J(2007)Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuitJournal of Electronics (China)10.1007/s11767-005-0170-224:2(225-231)Online publication date: 1-Mar-2007
https://doi.org/10.1007/s11767-005-0170-2

Adiabatic CMOS gate and adiabatic circuit design for low-power applications
1. Hardware

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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Wisetphanichkij SDejhan K(2009)The Combinational and Sequential Adiabatic Circuit Design and Its ApplicationsCircuits, Systems, and Signal Processing10.1007/s00034-009-9096-528:4(523-534)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1007/s00034-009-9096-5
Wang PYu J(2007)Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuitJournal of Electronics (China)10.1007/s11767-005-0170-224:2(225-231)Online publication date: 1-Mar-2007
https://doi.org/10.1007/s11767-005-0170-2

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Ultralow-power adiabatic circuit semi-custom design

Design of Ternary Adiabatic Dual-Rail Domino Comparator

Low Power Quaternary CMOS Circuit Design

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