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Wake-up protocols for controlling current surges in MTCMOS-based technology

Published: 18 January 2005 Publication History

Abstract

This paper proposes strategies to control the wake-up noise for circuits implemented in MTCMOS technology. In MTCMOS circuits, during the switchings between the active and standby modes, sudden surges in current happens due to floating voltages at the nodes. These surges might violate the reliability of the circuit. In this paper we address the above problem by developing wake-up strategies to control these current surges as the circuit is getting turned on. Through gradually turning on a circuit a smaller current will be drawn from the power-grid network. A novel partitioning technique is proposed for MTCMOS circuits under a given constraint of maximum drawn-current from the power-grid network. Two approaches are proposed in this paper; the optimal ILP-based formulation and a polynomial-time heuristic. Experimental results show that up to 90.7% improvement in peak drawn-current is obtained with a maximum of 4 clock cycles time to turn on the circuit. Also result show the effectiveness of the heuristic in terms of the quality of solution and a run-time of up to 6600 times faster than the ILP approach for larger circuits.

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Cited By

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  • (2024)ML-INSIGHT: Machine Learning for Inrush Current Prediction and Power Switch Network ImprovementProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670807(1-6)Online publication date: 5-Aug-2024
  • (2018)Power-up sequence control for MTCMOS designsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218768921:3(413-423)Online publication date: 29-Dec-2018
  • (2018)Power Gating Aware Task Scheduling in MPSoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205590719:10(1801-1812)Online publication date: 29-Dec-2018
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  1. Wake-up protocols for controlling current surges in MTCMOS-based technology

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    cover image ACM Conferences
    ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
    January 2005
    1495 pages
    ISBN:0780387376
    DOI:10.1145/1120725
    • General Chair:
    • Ting-Ao Tang
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 18 January 2005

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    View all
    • (2024)ML-INSIGHT: Machine Learning for Inrush Current Prediction and Power Switch Network ImprovementProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670807(1-6)Online publication date: 5-Aug-2024
    • (2018)Power-up sequence control for MTCMOS designsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218768921:3(413-423)Online publication date: 29-Dec-2018
    • (2018)Power Gating Aware Task Scheduling in MPSoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.205590719:10(1801-1812)Online publication date: 29-Dec-2018
    • (2018)Design of General Purpose Microprocessor with an Improved Performance Self-Sleep Circuit2018 International Conference on Smart Systems and Inventive Technology (ICSSIT)10.1109/ICSSIT.2018.8748868(419-424)Online publication date: Dec-2018
    • (2016)An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252391635:10(1730-1743)Online publication date: 1-Oct-2016
    • (2009)On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground NoiseProceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2009.54(109-114)Online publication date: 13-May-2009
    • (2008)Power gating scheduling for power/ground noise reductionProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391716(980-985)Online publication date: 8-Jun-2008

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