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On multiple-voltage high-level synthesis using algorithmic transformations

Published: 18 January 2005 Publication History

Abstract

This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the minimum achieved sample period (MASP) as much as possible. The minimization of MASP results in high task mobilities. Thereafter, we can assign tasks with high mobilities to low-voltage components and minimize energy dissipation under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. For instance, as the experimental results, we can save the power consumption up to 54.77% for the case of the third-order IIR filter.

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  • (2014)Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock GatingIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.7.747(74-80)Online publication date: 2014
  • (2013)Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented SchedulingIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.6.1016(101-111)Online publication date: 2013
  • (2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 January 2005

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Author Tags

  1. high-level synthesis
  2. loop shrinking
  3. low power circuit
  4. multiple voltage scheduling
  5. retiming
  6. unfolding

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Cited By

View all
  • (2014)Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock GatingIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.7.747(74-80)Online publication date: 2014
  • (2013)Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented SchedulingIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.6.1016(101-111)Online publication date: 2013
  • (2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
  • (2013)A fragmentation aware High-Level Synthesis flow for low power heterogenous datapathsIntegration, the VLSI Journal10.1016/j.vlsi.2012.02.00546:2(119-130)Online publication date: 1-Mar-2013
  • (2012)MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architecturesIEICE Electronics Express10.1587/elex.9.14149:17(1414-1422)Online publication date: 2012
  • (2011)Power optimization in heterogenous datapaths2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763226(1-6)Online publication date: Mar-2011
  • (2009)Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413110(491-497)Online publication date: Oct-2009
  • (2008)Restricted Chaining and Fragmentation Techniques in Power Aware High Level SynthesisProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.120(267-273)Online publication date: 3-Sep-2008
  • (2007)Algorithmic transformations and peak power constraint applied to multiple-voltage low-power VLSI signal processingWSEAS Transactions on Signal Processing10.5555/1486764.14867653:12(479-486)Online publication date: 1-Dec-2007

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