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- Akasaka HAbe SYanagisawa MTogawa N(2013)Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented SchedulingIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.6.1016(101-111)Online publication date: 2013
- ABE SSHI YUSAMI KYANAGISAWA MTOGAWA N(2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
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