Article

Statistical clock tree routing for robustness to process variations

Authors:

Uday Padmanabhan,

Jiang HuAuthors Info & Claims

ISPD '06: Proceedings of the 2006 international symposium on Physical design

Pages 149 - 156

https://doi.org/10.1145/1123008.1123037

Published: 09 April 2006 Publication History

Abstract

Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high speed, large area clock networks. To achieve multi-GHz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. We propose statistical centering based clock routing algorithm built upon DME that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by: i) choosing the best center measure which is dynamically based on the first three moments of the skew distribution, and ii) designing for all sink pairs in the subtrees simultaneously. In addition, a variation aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate the efficiency of the proposed method in reducing the number of skew violations by 12%-37%.

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Cited By

Lung CZeng ZChou CChang SDe Micheli GAl-Hashimi BMueller WMacii E(2010)Clock skew optimization considering complicated power modesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871280(1474-1479)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871280
Chiao-Ling Lung Zi-Yi Zeng Chung-Han Chou Shih-Chieh Chang (2010)Clock skew optimization considering complicated power modes2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)10.1109/DATE.2010.5457044(1474-1479)Online publication date: Mar-2010
https://doi.org/10.1109/DATE.2010.5457044
Pan DCho MKyung CChoi KHa S(2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356860(220-225)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356860
Show More Cited By

Index Terms

Statistical clock tree routing for robustness to process variations
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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cover image ACM Conferences

ISPD '06: Proceedings of the 2006 international symposium on Physical design

April 2006

232 pages

ISBN:1595932992

DOI:10.1145/1123008

General Chair:
Lou Scheffer
Cadence

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 April 2006

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April 9 - 12, 2006

California, San Jose, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Lung CZeng ZChou CChang SDe Micheli GAl-Hashimi BMueller WMacii E(2010)Clock skew optimization considering complicated power modesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871280(1474-1479)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871280
Chiao-Ling Lung Zi-Yi Zeng Chung-Han Chou Shih-Chieh Chang (2010)Clock skew optimization considering complicated power modes2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)10.1109/DATE.2010.5457044(1474-1479)Online publication date: Mar-2010
https://doi.org/10.1109/DATE.2010.5457044
Pan DCho MKyung CChoi KHa S(2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356860(220-225)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356860
Padmanabhan UWang JHu J(2008)Robust Clock Tree Routing in the Presence of Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92577627:8(1385-1397)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1109/TCAD.2008.925776
Chia-Chun Tsai Wei-Shi Lin Jan-Ou Wu Chung-Chieh Kuo Trong-Yen Lee (2008)Layer assignment considering manufacturability in X-architecture clock tree2008 8th IEEE International Conference on Computer and Information Technology10.1109/CIT.2008.4594790(880-885)Online publication date: Jul-2008
https://doi.org/10.1109/CIT.2008.4594790
Pan DMinsik Cho (2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond2008 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2008.4483945(220-225)Online publication date: Jan-2008
https://doi.org/10.1109/ASPDAC.2008.4483945
Pan DYu PCho MRamalingam AKim KRajaram AShi S(2008)Design for manufacturing meets advanced process control: A surveyJournal of Process Control10.1016/j.jprocont.2008.04.00718:10(975-984)Online publication date: Dec-2008
https://doi.org/10.1016/j.jprocont.2008.04.007
Yu HHu YLiu CHe LMadden PPan D(2007)Minimal skew clock embedding considering time variant temperature gradientProceedings of the 2007 international symposium on Physical design10.1145/1231996.1232036(173-180)Online publication date: 18-Mar-2007
https://dl.acm.org/doi/10.1145/1231996.1232036

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