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A faster implementation of APlace

Published: 09 April 2006 Publication History

Abstract

APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and density approximation functions. We speed up the placer using a hybrid usage of wirelength and density approximaions during he course of multi-level placement, and obtain 2-2.5 imes speedup of global placement on the IBM ISPD04 and ISPD05 benchmarks. Recent applications of the APlace framework to supply voltage degradation-aware placement and lens aberration-aware timing-driven placement are also briefly described.

References

[1]
T.F. Chan,J. Cong and K. Sze, "Multilevel Generalized Force-directed Method for Circuit Placement," in Proc. ACM/IEEE International Symposium on Physical Design 2005, pp. 185--192.
[2]
A.B. Kahng and Q. Wang, "Implementation and Extensibility of an Analytic Placer," IEEE Transactions on Computer-Aided Design 24(5)(2005), pp. 734--747.
[3]
A.B. Kahng, S. Reda, and Q. Wang, "APlace: A General Analytic Placemen Framework," in Proc. ACM/IEEE International Symposium on Physical Design 2005, pp. 233--235.
[4]
A.B. Kahng, S. Reda, and Q. Wang, "Architecture and Details of a High Quality, Large-Scale Analytical Placer," in Proc. Int. Conf. Computer Aided Design 2005, pp. 891--898.
[5]
A.B. Kahng, B. Liu, and Q. Wang, "Supply Voltage Degradation Aware Analytical Placement," in Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design 2005, pp. 437--443.
[6]
A.B. Kahng, C.-H. Park, P. Sharma and Q. Wang, "Lens Aberration-Aware Timing-Driven Placement," in Proc. Design Automation and Testing in Europe 2006, to appear.
[7]
A.A. Kennings and I.L. Markov, "Analytical Minimization of Half-Perimeter Wirelength ", Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 179--184.
[8]
W. Naylor, "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer," US Patent 6301693, 2001.
[9]
G. Sigl, K. Doll and F.M. Johannes, "Analytical Placement: A Linear or a Quadratic Objective Function?," in Proc. ACM/IEEE Design Automation Conf., 1991, pp. 427--431.
[10]
N. Viswanathan and C. Chu, "FastPlace: Efficient Analytical Placemen Using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," in Proc. ACM/IEEE International Symposium on Physical Design 2004, pp.26--33.

Cited By

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  • (2024)Pplace-MS: Methodologically Faster Poisson’s Equation-Based Mixed-Size Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062843:2(613-626)Online publication date: Feb-2024
  • (2023)The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299868(1-6)Online publication date: 10-Sep-2023
  • (2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
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cover image ACM Conferences
ISPD '06: Proceedings of the 2006 international symposium on Physical design
April 2006
232 pages
ISBN:1595932992
DOI:10.1145/1123008
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 April 2006

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Author Tags

  1. analytical placement
  2. lens aberration
  3. scalability
  4. supply voltage degradation

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ISPD06
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ISPD06: International Symposium on Physical Design 2006
April 9 - 12, 2006
California, San Jose, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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International Symposium on Physical Design
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Cited By

View all
  • (2024)Pplace-MS: Methodologically Faster Poisson’s Equation-Based Mixed-Size Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332062843:2(613-626)Online publication date: Feb-2024
  • (2023)The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299868(1-6)Online publication date: 10-Sep-2023
  • (2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
  • (2023)On a Moreau Envelope Wirelength Model for Analytical Global Placement2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247712(1-6)Online publication date: 9-Jul-2023
  • (2023)Mitigating Distribution Shift for Congestion Optimization in Global Placement2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247660(1-6)Online publication date: 9-Jul-2023
  • (2022)Deep Learning Framework for PlacementMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_9(221-245)Online publication date: 10-Aug-2022
  • (2022)Global and Detailed PlacementVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_4(95-130)Online publication date: 15-Jun-2022
  • (2021)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300384340:4(748-761)Online publication date: Apr-2021
  • (2021)Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643544(1-8)Online publication date: 1-Nov-2021
  • (2021)DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643441(1-8)Online publication date: 1-Nov-2021
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