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Effective techniques for the generalized low-power binding problem

Published: 01 January 2006 Publication History

Abstract

This article proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First, the generalized low power binding problem is formulated as an Integer Linear Programming (ILP) problem that happens to be an NP-complete task to solve. Then two polynomial-time heuristics are proposed that provide a speedup of up to 13.7 with an extremely low penalty for power when compared to the optimal ILP solution for our selected benchmarks.

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cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 11, Issue 1
January 2006
250 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/1124713
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 January 2006
Published in TODAES Volume 11, Issue 1

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Author Tags

  1. Low-power binding
  2. graph theory
  3. high level synthesis

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  • (2019)Fast FPGA prototyping for real-time image processing with very high-level synthesisJournal of Real-Time Image Processing10.1007/s11554-017-0688-116:5(1795-1812)Online publication date: 1-Oct-2019
  • (2017)Energy aware synthesis of application kernels through composition of data-paths on a CGRAIntegration10.1016/j.vlsi.2017.02.00958(320-328)Online publication date: Jun-2017
  • (2013)SAT based low power binding to reduce switching activity2013 Sixth International Conference on Contemporary Computing (IC3)10.1109/IC3.2013.6612185(175-180)Online publication date: Aug-2013
  • (2012)A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapathsVLSI Design10.1155/2012/2732762012(2-2)Online publication date: 1-Jan-2012
  • (2011)Wire Planning for Electromigration and Interference Avoidance in Analog CircuitsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.2402E94-A:11(2402-2411)Online publication date: 2011
  • (2011)A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of DatapathsProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.55(290-295)Online publication date: 4-Jul-2011
  • (2011)High level synthesis of data flow graphs using integer linear programming for switching power reduction2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies10.1109/ICSCCN.2011.6024597(475-479)Online publication date: Jul-2011
  • (2009)FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimationProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630125(838-843)Online publication date: 26-Jul-2009

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