article

ILP models for simultaneous energy and transient power minimization during behavioral synthesis

Authors:

Saraju P. Mohanty,

N. Ranganathan,

Sunil K. ChappidiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 1

Pages 186 - 212

https://doi.org/10.1145/1124713.1124725

Published: 01 January 2006 Publication History

Abstract

In low-power design for battery-driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a CMOS circuit, which is predominant compared to static power dissipation for higher switching activity. The peak power, the cycle difference power, and the peak power differential drive the transient characteristic of a CMOS circuit. In this article, we propose an ILP-based framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called “modified cycle power function” (CPF*) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILP-based datapath scheduling schemes with CPF* as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected high-level synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained.

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Cited By

Esmaeili MZahiri SRazavi S(2021)An efficient CAD tool for High-Level Synthesis of VLSI digital transformersSignal and Data Processing10.52547/jsdp.18.3.318:3(3-18)Online publication date: 1-Dec-2021
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ILP models for simultaneous energy and transient power minimization during behavioral synthesis

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 1

January 2006

250 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1124713

Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 January 2006

Published in TODAES Volume 11, Issue 1

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Cited By

Esmaeili MZahiri SRazavi S(2021)An efficient CAD tool for High-Level Synthesis of VLSI digital transformersSignal and Data Processing10.52547/jsdp.18.3.318:3(3-18)Online publication date: 1-Dec-2021
https://doi.org/10.52547/jsdp.18.3.3
Strobel MRadetzki M(2019)Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip DesignACM Transactions on Embedded Computing Systems10.1145/335658318:5(1-25)Online publication date: 9-Oct-2019
https://dl.acm.org/doi/10.1145/3356583
Wu TKao THuang SLi TLin HLin Y(2010)Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899828(444-449)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899828
WU TKAO TLIN H(2010)Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC DesignsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E93.A.2581E93-A:12(2581-2589)Online publication date: 2010
https://doi.org/10.1587/transfun.E93.A.2581
Chen SYao YYoshimura T(2010)A dynamic programming based algorithm for post-scheduling frequency assignment in energy-efficient high-level synthesis2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology10.1109/ICSICT.2010.5667427(797-799)Online publication date: Nov-2010
https://doi.org/10.1109/ICSICT.2010.5667427
Tsung-Yi Wu Tzi-Wei Kao Shi-Yi Huang Tai-Lun Li How-Rern Lin (2010)Combined use of rising and falling edge triggered clocks for peak current reduction in IP-Based SoC designs2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419842(444-449)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419842
Liu YWu K(2009)An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer LevelProceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2009.19(349-357)Online publication date: 7-Oct-2009
https://dl.acm.org/doi/10.1109/DFT.2009.19
Mohanty S(2008)ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479721(174-177)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479721
Wang JPan XWang JSun K(2007)Fast combination of scheduling chains under resource and time constraintsJournal of Zhejiang University-SCIENCE A10.1631/jzus.2007.A01198:1(119-126)Online publication date: 1-Jan-2007
https://doi.org/10.1631/jzus.2007.A0119

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