Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology
Pages 123 - 126
Abstract
The V-NPN transistor in deep n-well CMOS process has small flicker noise. The proposed three-stage operational amplifier uses parallel connection V-NPN as input differential pair for low noise. However, the only significant disadvantage of V-NPN transistor as compared to MOSFET transistor is input bias current, which will result in input current noise. For overcoming this effect, a novel input bias current cancellation circuit has been proposed in this work for high precision. The proposed operational amplifier has combined low noise and high precision performance. Good noise performance 2.04nV/ at baseband has been achieved, and flicker noise corner frequency is about 1.78KHz. Moreover input bias current is almost negligible. The relatively high operating current of the input stage reduces voltage noise and increases gain bandwidth. 1.6GHz gain bandwidth with 68-degree phase margin is adequate for high frequency analog application.
References
[1]
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis and Robert G. Meyer, Analysis and design of analog integrated circuits, 4th ed., John Wiley & Sons, Inc, 2001.
[2]
W. T. Holman, J. A. Connelly, J. O. Perez, and C. D. Motchenbacher, "A low noise CMOS operational amplifier in a 1.2?m digital technology", Proc. 35th Midwest Symp. Circuits Syst, Aug 1992, pp.1120--1123.
[3]
Kaila G. Lamb, Steven J. Sanchez, and W. Timothy Holman, "A low noise operational amplifier design using sub-threshold operation", Proc. of 40th Midwest symposium on circuits and systems, Sacramento, CA, 1997, pp.35--38.
[4]
W. Timothy Holman and J. Alvin Connelly, "A compact low noise operational amplifier for a 1.2?m digital CMOS technology", IEEE Journal of Solid-State Circuits, Vol.30, No.6, June 1995, pp.710--714.
[5]
SMIC documentation no. TD-MM18-DR-2001V2P.
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Ilku Nam, and Kwyro Lee, "High-Performance RF Mixer and Operational Amplifier BiCMOS Circuits Using Parasitic Vertical Bipolar Transistor in CMOS Technology", IEEE Journal of Solid-State Circuits, Vol.40, No.2, February 2005, pp.392--402.
[7]
George Erdi, "Amplifier techniques for combining low noise, precision, and high-speed performance", IEEE Journal of Solid-State Circuits, Vol. sc-16, No.6, December 1981, pp.653--661.
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Peter R. Kinget, "Device Mismatch and Tradeoffs in the Design of Analog Circuits", IEEE Journal of Solid-State Circuits, Vol.40, No.6, June 2005, pp.1212--1224.
Index Terms
- Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology
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Published In
April 2006
450 pages
ISBN:1595933476
DOI:10.1145/1127908
- General Chairs:
- Gang Qu,
- Yehea Ismail,
- Program Chairs:
- Vijaykrishnan Narayanan,
- Hai Zhou
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Published: 30 April 2006
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