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Optimizing noise-immune nanoscale circuits using principles of Markov random fields

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A. ZaslavskyAuthors Info & Claims

GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

Pages 149 - 152

https://doi.org/10.1145/1127908.1127945

Published: 30 April 2006 Publication History

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Abstract

As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS offers a possible solution. In this work, we present a new area and power efficient design methodology for the implementation of a probabilistic framework into CMOS technology based on Markov Random Fields (MRF). Using SPICE, we simulate elementary logic components and sample circuits from the MCNC'91 benchmark set and show the area and power benefits compared to older MRF mapping strategies. We also extend our area and power efficient approach to improving the design of a Hamming decoder based on MRF principles.

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Cited By

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Li YHu JLu HChen J(2021)Area-efficient partial-clique-energy MRF pair design with ultra-low supply voltage2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527220(261-264)Online publication date: 11-Mar-2021
https://dl.acm.org/doi/10.1109/ISCAS.2016.7527220
Li YLi YWey ICheng DYang FZeng XChen J(2020)Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic LogicIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2019.294502430:10(3803-3813)Online publication date: Oct-2020
https://doi.org/10.1109/TCSVT.2019.2945024
Li YLi YWey IHu JYang FZeng XJiang XChen J(2018)Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF MethodIEEE Journal of Solid-State Circuits10.1109/JSSC.2018.283446453:8(2389-2398)Online publication date: Aug-2018
https://doi.org/10.1109/JSSC.2018.2834464
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Index Terms

Optimizing noise-immune nanoscale circuits using principles of Markov random fields
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

April 2006

450 pages

ISBN:1595933476

DOI:10.1145/1127908

General Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University
,
Program Chairs:
Vijaykrishnan Narayanan
Pennsylvania State University
,
Hai Zhou
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 30 April 2006

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April 30 - May 1, 2006

PA, Philadelphia, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Li YHu JLu HChen J(2021)Area-efficient partial-clique-energy MRF pair design with ultra-low supply voltage2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527220(261-264)Online publication date: 11-Mar-2021
https://dl.acm.org/doi/10.1109/ISCAS.2016.7527220
Li YLi YWey ICheng DYang FZeng XChen J(2020)Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic LogicIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2019.294502430:10(3803-3813)Online publication date: Oct-2020
https://doi.org/10.1109/TCSVT.2019.2945024
Li YLi YWey IHu JYang FZeng XJiang XChen J(2018)Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF MethodIEEE Journal of Solid-State Circuits10.1109/JSSC.2018.283446453:8(2389-2398)Online publication date: Aug-2018
https://doi.org/10.1109/JSSC.2018.2834464
I-Chyn Wey Po-Jen Lin Bing-Chen Wu Chien-Chang Peng Pin-Hsi Lin (2014)Near-threshold-voltage circuit design: The design challenges and chances2014 International SoC Design Conference (ISOCC)10.1109/ISOCC.2014.7087666(138-141)Online publication date: Nov-2014
https://doi.org/10.1109/ISOCC.2014.7087666
Wey IShen Y(2014)Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuitsIntegration10.1016/j.vlsi.2013.12.00347:4(431-442)Online publication date: Sep-2014
https://doi.org/10.1016/j.vlsi.2013.12.003
Liu KAn TCai HNaviner LNaviner JPetit H(2013)A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technologyEurocon 201310.1109/EUROCON.2013.6625225(1829-1836)Online publication date: Jul-2013
https://doi.org/10.1109/EUROCON.2013.6625225
Liu KCai HAn TNaviner LNaviner JPetit H(2013)Reliability analysis of combinational circuits with the influences of noise and single-event transients2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)10.1109/DFT.2013.6653609(218-223)Online publication date: Oct-2013
https://doi.org/10.1109/DFT.2013.6653609
Wey ILan YPeng C(2013)Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch designMicroelectronics Reliability10.1016/j.microrel.2013.06.00253:12(2057-2069)Online publication date: Dec-2013
https://doi.org/10.1016/j.microrel.2013.06.002
Wey IChen YYu CAndyWu AChen J(2009)Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuitsIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.201564856:11(2411-2424)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1109/TCSI.2009.2015648
Patil NDeng JLin AWong HMitra S(2008)Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200327827:10(1725-1736)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1109/TCAD.2008.2003278
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Abstract

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Designing logic circuits for probabilistic computation in the presence of noise

Designing Nanoscale Logic Circuits Based on Markov Random Fields

Utilizing reverse short-channel effect for optimal subthreshold circuit design

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