William R. Roberts
ABSTRACT
Violations of the timing constraints in a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.
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Index Terms
- Effects of process and environmental variations on timing characteristics of clocked registers
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