skip to main content
10.1145/1127908.1127960acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

A design flow to optimize circuit delay by using standard cells and PLAs

Published: 30 April 2006 Publication History

Abstract

This paper presents a design flow that optimizes a standard cell based circuit for performance by implementing critical paths in a Programmable Logic Array (PLA). Given a standard-cell based circuit as input, our approach iteratively extracts critical paths from this circuit, which are then implemented using a PLA circuit. PLAs are a good candidate for such an approach, since they exhibit a gradual increase in delay as additional vectors are added. In subsequent iterations, these critical paths are treated as don't cares, allowing the standard cell based design to be simplified after each iteration. The final design consists of a portion which is implemented using a PLA, and another portion which is implemented using standard cells. We demonstrate that on average, our approach can achieve about 22.5% improvement in the SPICE based delay of a design, along with a placed-and-routed area improvement of 11%.

References

[1]
S. P. Khatri, Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics. PhD thesis, UC Berkeley, Dec 1999.
[2]
S. Khatri, R. Brayton, and A. Sangiovanni-Vincentelli, "Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric," in Proceedings, IEEE/ACM International Conference on Computer Aided Design, pp. 412--418, Nov 2000.
[3]
N. Jayakumar and S. Khatri, "A METAL and VIA maskset programmable VLSI design methodology using PLAs," in IEEE/ACM International Conference on Computer Aided Design, pp. 590--594, Nov 2004.
[4]
P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, ch. Delay Models and Exact Timing Analysis, pp. 167--189. Kluwer Academic Publishers, 1993.
[5]
J. P. Fishburn, "A depth-decreasing heuristic for combinational logic: Or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between.," in DAC, pp. 361--364, 1990.
[6]
K. J. Singh, A. R. Wang, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Timing Optimization of Combinational Logic," in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 282--285, Nov. 1988.
[7]
C. L. Berman, D. J. Hathaway, A. S. LaPaugh, and L. H. Trevillyan, "Efficient techniques for timing correction," in ISCAS, pp. 415--419, 1990.
[8]
P. McGeer, A. Saldanha, P. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Timing Analysis and Delay-Fault Test Generation using Path Recursive Functions," in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 180--183, Nov. 1991.
[9]
S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, P. Hofstee, D. LaPotin, K. Lee, D. Meltzer, H. Ngo, K. Nowka, J. Silberman, O. Takahashi, and I. Vo, "Design methodology for a 1.0 ghz microprocessor," in Proceedings of the International Conference on Computer Design (ICCD), pp. 17--23, Oct 1998.
[10]
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May 1992.
[11]
R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
[12]
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.
[13]
N. Jayakumar and S. Khatri, "A variation-tolerant sub-threshold design approach," in Proceedings, Design Automation Conference, (Anaheim, CA), June 2005.
[14]
F. Mo and R. Brayton, "PLA-based regular structures and their synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 723--729, June 2003.
[15]
F. Mo and R. Brayton, "River PLAs: a regular circuit structure," in Proceedings, Design Automation Conference, pp. 201--206, June 2002.
[16]
F. Mo and R. Brayton, "Whirlpool PLAs: a regular logic structure and their synthesis," in IEEE/ACM International Conference on Computer Aided Design, pp. 543--550, Nov 2002.
[17]
L. Nagel, "Spice: A computer program to simulate computer circuits," in University of California, Berkeley UCB/ERL Memo M520, May 1995.
[18]
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. of IEEE Custom Integrated Circuit Conference, pp. 201--204, Jun 2000. http://www-device.eecs.berkeley.edu/~ptm.
[19]
Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA, Envisia Silicon Ensemble Place-and-route Reference, Nov 1999.

Cited By

View all
  • (2008)Pipelined network of PLA based circuit designProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366162(213-218)Online publication date: 4-May-2008
  • (2008)Programmable Logic ArraysWiley Encyclopedia of Computer Science and Engineering10.1002/9780470050118.ecse316Online publication date: 15-Jan-2008
  • (2007)Structured and tuned array generation (STAG) for high-performance random logicProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228849(257-262)Online publication date: 11-Mar-2007

Index Terms

  1. A design flow to optimize circuit delay by using standard cells and PLAs

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI
    April 2006
    450 pages
    ISBN:1595933476
    DOI:10.1145/1127908
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 30 April 2006

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. PLA
    2. standard cell

    Qualifiers

    • Article

    Conference

    GLSVLSI06
    Sponsor:
    GLSVLSI06: Great Lakes Symposium on VLSI 2006
    April 30 - May 1, 2006
    PA, Philadelphia, USA

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 20 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2008)Pipelined network of PLA based circuit designProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366162(213-218)Online publication date: 4-May-2008
    • (2008)Programmable Logic ArraysWiley Encyclopedia of Computer Science and Engineering10.1002/9780470050118.ecse316Online publication date: 15-Jan-2008
    • (2007)Structured and tuned array generation (STAG) for high-performance random logicProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228849(257-262)Online publication date: 11-Mar-2007

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media