Joonsoo Kim
ABSTRACT
We describe a formal probabilistic power-performance design space exploration technique. The technique aims at enabling hierarchical design space exploration based on a fully probabilistic description of power-performance tradeoffs. Probabilistic Pareto sets in power-performance space are proposed as canonical encodings of the power and delay tradeoffs in designs under any source of uncertainty. An algorithm to compute a composite probabilistic power-performance Pareto set for series or parallel connections of circuit blocks is also developed and validated. The algorithm is based on numerical convolution and is suitable for micro-architecture pipeline design exploration in the presence of process variability.
- K. Nose and T. Sakurai, "Optimization of Vdd and Vth for Low-Power and High-Speed Application," ASP-DAC, 2000. Google Scholar
Digital Library
- M. Hamada, Y. Ootaguro, and T. Kuroda, "Utilizing surplus timing for power reduction," Proc. Custom Integrated Circuits Conf., 2001.Google Scholar
- X. Bai, C. Visweswariah, and P. N. Strenski, "Uncertainty-Aware Circuit Optimization," DAC, 2002. Google ScholarDigital Library
- C. Visweswariah, "Death, taxes and failing chips," DAC, 2003. Google ScholarDigital Library
- A. Chandrakasan, W.J. Bowhill, and F. Fox, Design of high-performance microprocessor circuits, IEEE Press, 2001. Google ScholarDigital Library
- T. Karnik, S. Borkar, and V. De, "Sub-90 nm technologies challenges and opportunities for CAD," ICCAD, 2002. Google ScholarDigital Library
- R. Gonzalez, B. Gordon, and M.A. Horowitz, "Supply and Threshold Voltage Scaling for Low Power CMOS," IEEE J. Solid-State Circuits, Aug. 1997.Google ScholarCross Ref
- R. Brodersen et al., "Methods for True Power Minimization," ICCAD, 2002. Google ScholarDigital Library
- V. Zyuban and P. Strenski, "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Level," ISLPED, 2002. Google ScholarDigital Library
- D. Markovic et al., "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, Aug. 2004.Google ScholarCross Ref
- A. Srivastava et al, "Accurate and Efficient Gate-Level Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance," DAC, 2005. Google ScholarDigital Library
- M. Mani and M. Orshansky, "A New Statistical Optimization Algorithm for Gate Sizing," ICCD, 2004. Google ScholarDigital Library
- M. Mani, A. Devgan, and M. Orshansky, "An efficient algorithm for statistical minimization of total power under timing yield constraints," DAC, 2005. Google ScholarDigital Library
- R. Zimmermann, Computer Arithmetic: Principles, Architectures, and VLSI Design, Lecture Notes, 1999.Google Scholar
- Berkeley Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm.Google Scholar
- J. P. Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," ICCAD, 1985.Google Scholar
- G. Ascia, V. Catania, and M. Palesi, "A Framework for Design Space Exploration of Parameterized VLSI Systems," VLSI Design, 2002.Google Scholar
- D. Berleant and J. Zhang, "Using Pearson correlation to improve envelopes around the distributions of functions," Reliable Computing, 10(2), pp. 139--161, 2004.Google ScholarCross Ref
- W. S. Wang, V. Kreinovich, and M. Orshansky, "Static Timing Analysis Based on Partial and Distribution-Free Probabilistic Descriptions of Delay Uncertainty," Timing Analysis Workshop, 2006.Google Scholar
Index Terms
- Towards formal probabilistic power-performance design space exploration
Recommendations
Analyzing Energy-Time Tradeoff in Power Overprovisioned HPC Data Centers
IPDPSW '15: Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium WorkshopMinimizing energy and power consumption of large scale data centers is one of the biggest challenges faced by the high performance computing community. In an over provisioned data center, nodes are power capped to run below their Thermal Design Power (...
Towards formal evaluation and verification of probabilistic design
ICCAD '14: Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided DesignIn the nanometer regime of integrated circuit fabrication, device variability imposes serious challenges to the design of reliable systems. A new computation paradigm of approximate and probabilistic design has been proposed recently to accept design ...
Workload-Aware CPU Performance Scaling for Transactional Database Systems
SIGMOD '18: Proceedings of the 2018 International Conference on Management of DataNatural short term fluctuations in the load of transactional data systems present an opportunity for power savings. For example, a system handling 1000 requests per second on average can expect more than 1000 requests in some seconds, fewer in others. ...
Comments