Ali Bastani
ABSTRACT
This paper reviews the use of monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. Noise tolerance is shown to fall as skewing is increased. The tradeoffs are studied both at the gate level and in a mixed static/monotonic static CMOS design.
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Index Terms
- Monotonic static CMOS tradeoffs in sub-100nm technologies
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