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Circuit architecture for low-power race-free programmable logic arrays

Published: 30 April 2006 Publication History

Abstract

The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

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A. Alvandpour et al., "A sub-130-nm conditional keeper technique," IEEE J. Solid-State Circuits, 37, no. 5, pp. 633--638, May 2002.
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N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. 3rd ed., Addison-Wesley, NY, 2005.
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J. Haigh et al., "A Low-Power 2.5-GHz 90-nm Level 1 Cache and Memory Management Unit," IEEE J. Solid State Circuits, 40, pp. 1190--1199, May, 2005.
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J. Wang, C. Chang, and C. Yeh, "Analysis and Design of High-Speed and Low-Power CMOS PLAs," IEEE J. Solid State Circuits, 36, pp. 1250--1262, Aug. 2001.
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Cited By

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  • (2009)Low-Power Race-Free Programmable Logic ArraysIEEE Journal of Solid-State Circuits10.1109/JSSC.2009.201376444:3(935-946)Online publication date: Mar-2009
  • (2008)A New Domino Logic Synthesis ApproachProceedings of the 2008 International Conference on Internet Computing in Science and Engineering10.1109/ICICSE.2008.79(325-328)Online publication date: 28-Jan-2008
  • (2007)Structured and tuned array generation (STAG) for high-performance random logicProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228849(257-262)Online publication date: 11-Mar-2007

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  1. Circuit architecture for low-power race-free programmable logic arrays

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      cover image ACM Conferences
      GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI
      April 2006
      450 pages
      ISBN:1595933476
      DOI:10.1145/1127908
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 30 April 2006

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      Author Tags

      1. circuit timing
      2. low power
      3. programmable logic arrays

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      April 30 - May 1, 2006
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      Cited By

      View all
      • (2009)Low-Power Race-Free Programmable Logic ArraysIEEE Journal of Solid-State Circuits10.1109/JSSC.2009.201376444:3(935-946)Online publication date: Mar-2009
      • (2008)A New Domino Logic Synthesis ApproachProceedings of the 2008 International Conference on Internet Computing in Science and Engineering10.1109/ICICSE.2008.79(325-328)Online publication date: 28-Jan-2008
      • (2007)Structured and tuned array generation (STAG) for high-performance random logicProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228849(257-262)Online publication date: 11-Mar-2007

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