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Tile size selection for low-power tile-based architectures

Published: 03 May 2006 Publication History

Abstract

In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accomplished by distilling the architectural cost of tiles with different computational widths into a system metric we call the Granularity Indicator (GI). The GI is then compared against the communications exposed when algorithms are partitioned across multiple tiles. Through this comparison, the tile granularity that best fits a given set of algorithms can be determined, reducing the system power for that set of algorithms. When the GI analysis is applied to the Synchroscalar tile architecture[1], we find that Synchroscalar's already low power consumption can be further reduced by 14% when customized for execution of the 802.11a reciever. In addition, the GI can also be a used to evaluate tile size when considering multiple applications simultaneously, providing a convenient platform for hardware-software co-design.

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Cited By

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  • (2014)A Hybrid of Fixed-Size and Dynamic-Size Tile Algorithm for Panoramic View on Mobile DevicesAdvances in Computer Science and its Applications10.1007/978-3-642-41674-3_100(703-708)Online publication date: 2014
  • (2010)A cost-effective load-balancing policy for tile-based, massive multi-core packet processorsACM Transactions on Embedded Computing Systems10.1145/1698772.16987829:3(1-25)Online publication date: 5-Mar-2010
  • (2009)Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810294(201-207)Online publication date: Mar-2009
  • Show More Cited By

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    cover image ACM Conferences
    CF '06: Proceedings of the 3rd conference on Computing frontiers
    May 2006
    430 pages
    ISBN:1595933026
    DOI:10.1145/1128022
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 03 May 2006

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    Author Tags

    1. media processors
    2. multi-core processors

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    May 3 - 5, 2006
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    View all
    • (2014)A Hybrid of Fixed-Size and Dynamic-Size Tile Algorithm for Panoramic View on Mobile DevicesAdvances in Computer Science and its Applications10.1007/978-3-642-41674-3_100(703-708)Online publication date: 2014
    • (2010)A cost-effective load-balancing policy for tile-based, massive multi-core packet processorsACM Transactions on Embedded Computing Systems10.1145/1698772.16987829:3(1-25)Online publication date: 5-Mar-2010
    • (2009)Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810294(201-207)Online publication date: Mar-2009
    • (2008)Architecture and Evaluation of an Asynchronous Array of Simple ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0162-153:3(243-259)Online publication date: 1-Dec-2008

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