article

A survey of research and practices of Network-on-chip

Authors:

Tobias Bjerregaard,

Shankar MahadevanAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 38, Issue 1

Pages 1 - es

https://doi.org/10.1145/1132952.1132953

Published: 29 June 2006 Publication History

Abstract

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

References

[1]

Agarwal, A. 1999. The Oxygen project---Raw computation. Scientific American, 44--47.

[2]

Aggarwal, A. and Franklin, M. 2002. Hierarchical interconnects for on-chip clustering. In Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS). IEEE Computer Society, 602--609.

Digital Library

[3]

Ahonen, T., Sigenza-Tortosa, D. A., Bin, H., and Nurmi, J. 2004. Topology optimization for application-specific networks-on-chip. In International Workshop on System Level Interconnect Prediction (SLIP). ACM, 53--60.

Digital Library

[4]

Al-Tawil, K. M., Abd-El-Barr, M., and Ashraf, F. 1997. A survey and comparison of wormhole routing techniques in a mesh networks. IEEE Network 11, 38--45.

Digital Library

[5]

Amde, M., Felicijan, T., Edwards, A. E. D., and Lavagno, L. 2005. Asynchronous on-chip networks. IEE Proceedings of Computers and Digital Techniques 152, 273--283.

[6]

Andreasson, D. and Kumar, S. 2004. On improving best-effort throughput by better utilization of guaranteed-throughput channels in an on-chip communication system. In Proceeding of 22th IEEE Norchip Conference.

[7]

Andreasson, D. and Kumar, S. 2005. Slack-time aware routing in NoC systems. In International Symposium on Circuits and Systems (ISCAS). IEEE, 2353--2356.

[8]

Andriahantenaina, A. and Greiner, A. 2003. Micro-network for SoC: Implementation of a 32-port spin network. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition. IEEE, 1128--1129.

Digital Library

[9]

ARM. 2004. AMBA Advanced eXtensible Interface (AXI) Protocol Specification, Version 1.0. http://www.arm.com.

[10]

Arteris. 2005. A comparison of network-on-chip and busses. White paper. http://www.arteris. com/noc_whitepaper.pdf.

[11]

Bailey, D., Barszcz, E., Barton, J., Browning, D., Carter, R., Dagum, L., Fatoohi, R., Fineberg, S., Frederickson, P., Lasinski, T., Schreiber, R., Simon, H., Venkatakrishnan, V., and Weeratunga, S. 1994. RNR Tech. rep. RNR-94-007. NASA Ames Research Center.

[12]

Bainbridge, J. and Furber, S. 2002. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro 22, 5 (Oct.) 16--23.

Digital Library

[13]

Bainbridge, W. and Furber, S. 2001. Delay insensitive system-on-chip interconnect using 1-of-4 data encoding. In Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems (ASYNC). 118--126.

Digital Library

[14]

Banerjee, N., Vellanki, P., and Chatha, K. S. 2004. A power and performance model for network-on-chip architectures. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 1250--1255.

Digital Library

[15]

Beigne, E., Clermidy, F., Vivet, P., Clouard, A., and Renaudin, M. 2005. An asynchronous NOC architecture providing low latency service and its multi-level design framework. In Proceedings of the 11th International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 54--63.

Digital Library

[16]

Benini, L. and Micheli, G. D. 2001. Powering network-on-chips. In The 14th International Symposium on System Synthesis (ISSS). IEEE, 33--38.

Digital Library

[17]

Benini, L. and Micheli, G. D. 2002. Networks on chips: A new SoC paradigm. IEEE Comput. 35, 1 (Jan.), 70--78.

Digital Library

[18]

Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., and De Micheli, G. 2005. NoC synthesis flow for customized domain specific multiprocessor Systems-on-Chip. In IEEE Trans. Parall. Distrib. Syst. 113--129.

Digital Library

[19]

Bhojwani, P. and Mahapatra, R. 2003. Interfacing cores with on-chip packet-switched networks. In Proceedings of the 16th International Conference on VLSI Design. 382--387.

Digital Library

[20]

Bjerregaard, T. 2005. The MANGO clockless network-on-chip: Concepts and implementation. Ph.D. thesis, Informatics and Mathematical Modeling, Technical University of Denmark, Lyngby, Denmark.

[21]

Bjerregaard, T., Mahadevan, S., Olsen, R. G., and Sparsø, J. 2005. An OCP compliant network adapter for gals-based soc design using the MANGO network-on-chip. In Proceedings of International Symposium on System-on-Chip (ISSoC). IEEE.

[22]

Bjerregaard, T., Mahadevan, S., and Sparsø, J. 2004. A channel library for asynchronous circuit design supporting mixed-mode modeling. In Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). Springer, 301--310.

[23]

Bjerregaard, T. and Sparsø, J. 2005a. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 1226--1231.

Digital Library

[24]

Bjerregaard, T. and Sparsø, J. 2005b. A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In Proceedings of the 11th International Symposium on Advanced Resear. in Asynchronous Circuits and Systems. IEEE, 34--43.

Digital Library

[25]

Bogliolo, A. 2001. Encodings for high-performance energy-efficient signaling. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). 170--175.

Digital Library

[26]

Bolotin, E., Cidon, I., Ginosaur, R., and Kolodny, A. 2004. QNoC: QoS architecture and design process for network-on-chip. J. Syst. Archit. 50, 2-3, 105--128.

Digital Library

[27]

Catthoor, F., Cuomo, A., Martin, G., Groeneveld, P., Rudy, L., Maex, K., de Steeg, P. V., and Wilson, R. 2004. How can system level design solve the interconnect technology scaling problem. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 332--337.

Digital Library

[28]

Chapiro, D. 1984. Globally-asynchronous locally-synchronous systems. Ph.D. thesis (Report No. STAN-CS-84-1026) Stanford University.

Digital Library

[29]

Chelcea, T. and Nowick, S. M. 2001. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proceedings of the 38th Design Automation Conference (DAC). IEEE, 21--26.

Digital Library

[30]

Chiu, G.-M. 2000. The odd-even turn model for adaptive routing. IEEE Trans. Parall. Distrib. Syst. 11, 729--738.

Digital Library

[31]

Cole, R. J., Maggs, B. M., and Sitaraman, R. K. 2001. On the benefit of supporting virtual channels in wormhole routers. J. Comput. Syst. Sciences 62, 152--177.

Digital Library

[32]

Culler, D. E., Singh, J. P., and Gupta, A. 1998. Parallel Computer Architecture: A Hardware/Software Approach. 1st Ed. Morgan Kaufmann.

Digital Library

[33]

Dally, W. J. 1990. Performance analysis of k-ary n-cube interconnection networks. IEEE Trans. Comput. 39, 6 (June) 775--785.

Digital Library

[34]

Dally, W. J. 1992. Virtual-channel flow control. IEEE Trans. Parall. Distrib. Syst. 3, 2 (March) 194--205.

Digital Library

[35]

Dally, W. J. and Aoki, H. 1993. Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans. Parall. Distrib. Syst. 4, 4 (April) 466--475.

Digital Library

[36]

Dally, W. J. and Seitz, C. L. 1987. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36, 5 (May) 547--553.

Digital Library

[37]

Dally, W. J. and Towles, B. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference (DAC). IEEE, 684--689.

Digital Library

[38]

de Mello, A. V., Ost, L. C., Moraes, F. G., and Calazans, N. L. V. 2004. Evaluation of routing algorithms on mesh based nocs. Tech. rep., Faculdade de Informatica PUCRS---Brazil.

[39]

Dick, R. 2002. Embedded system synthesis benchmarks suite. http://www.ece.northwestern.edu/dickrp/e3s/.

[40]

Dielissen, J., Radulescu, A., Goossens, K., and Rijpkema, E. 2003. Concepts and implementation of the phillips network-on-chip. In Proceedings of the IP based SOC (IPSOC). IFIP.

[41]

Dobbelaere, I., Horowitz, M., and Gamal, A. E. 1995. Regenerative feedback repeaters for programmable interconnections. IEEE J. Solid-State Circuits 30, 11 (Nov.) 1246--1253.

[42]

Dobkin, R., Ginosaur, R., and Sotiriou, C. P. 2004. Data synchronization issues in GALS SoCs. In Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems. IEEE, 170--179.

[43]

Duato, J. 1993. A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parall. Distrib. Syst. 4, 12 (Dec.) 1320--1331.

Digital Library

[44]

Duato, J. 1995. A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parall. Distrib. Syst. 6, 10 (Oct.) 1055--1067.

Digital Library

[45]

Duato, J. 1996. A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans. Parall. Distrib. Syst. 7, 8 (Aug.) 841--854.

Digital Library

[46]

Duato, J. and Pinkston, T. M. 2001. A general theory for deadlock-free adaptive routing using a mixed set of resources. IEEE Trans. Parall. Distrib. Syst. 12, 12 (Dec.) 1219--1235.

Digital Library

[47]

Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering Approach. Morgan Kaufmann.

Digital Library

[48]

Felicijan, T., Bainbridge, J., and Furber, S. 2003. An asynchronous low latency arbiter for quality of service (QoS) applications. In Proceedings of the 15th International Conference on Microelectronics (ICM). IEEE, 123--126.

[49]

Felicijan, T. and Furber, S. B. 2004. An asynchronous on-chip network router with quality-of-service (QoS) support. In Proceedings IEEE International SOC Conference. IEEE, 274--277.

[50]

Fitzpatrick, T. 2004. System verilog for VHDL users. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE Computer Society, 21334.

Digital Library

[51]

Forsell, M. 2002. A scalable high-performance computing solution for networks on chips. IEEE Micro 22, 5, 46--55.

Digital Library

[52]

Gaughan, P. T., Dao, B. V., Yalamanchili, S., and Schimmel, D. E. 1996. Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks. IEEE Trans. Comput. 45, 6 (June) 651--665.

Digital Library

[53]

Genko, N., Atienza, D., De Micheli, G., Benini, L., Mendias, J., Hermida, R., and Catthoor, F. 2005. A novel approach for network on chip emulation. In International Symposium on Circuits and Systems (ISCAS). IEEE, 2365--2368.

[54]

Gerstlauer, A. 2003. Communication abstractions for system-level design and synthesis. Tech. Rep. TR-03-30, Center for Embedded Computer Systems, University of California, Irvine, CA.

[55]

Ginosaur, R. 2003. Fourteen ways to fool your synchrononizer. In Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems. IEEE, 89--96.

Digital Library

[56]

Glass, C. J. and Ni, L. M. 1994. The turn model for adaptive routing. J. ACM 41, 874--902.

Digital Library

[57]

Goossens, K., Dielissen, J., Gangwal, O. P., Pestana, S. G., Radulescu, A., and Rijpkema, E. 2005. A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 1182--1187.

Digital Library

[58]

Goossens, K., Dielissen, J., and Radulescu, A. 2005. Æthereal network on chip: Concepts, architectures and implementations. IEEE Design Test Comput. 22, 5, 414--421.

Digital Library

[59]

Goossens, K., Meerbergen, J. V., Peeters, A., and Wielage, P. 2002. Networks on silicon: Combining best-effort and guaranteed services. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 196--200.

Digital Library

[60]

Guerrier, P. and Greiner, A. 2000. A generic architecture for on-chip packet-switched interconnections. In Proceedings of the Design Automation and Test in Europe (DATE). IEEE, 250--256.

Digital Library

[61]

Guo, M., Nakata, I., and Yamashita, Y. 2000. Contention-free communication scheduling for array redistribution. Parall. Comput. 26, 1325--1343.

Digital Library

[62]

Hansson, A., Goossens, K., and Radulescu, A. 2005. A unified approach to constrained mapping and routing on networks-on-chip architectures. In CODES/ISSS. ACM/IEEE, 75--80.

Digital Library

[63]

Harmanci, M., Escudero, N., Leblebici, Y., and Ienne, P. 2005. Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 1782--1785.

[64]

Hauck, S. 1995. Asynchronous design methodologies: an overview. Proceedings of the IEEE 83, 1 (Jan.) 69--93.

[65]

Havemann, R. H. and Hutchby, J. A. 2001. High-performance interconnects: An integration overview. Proceedings of the IEEE 89, 5 (May) 586--601.

[66]

Haverinen, A., Leclercq, M., Weyrich, N., and Wingard, D. 2002. SystemC based SoC communication modeling for the OCP protocol. White paper. http://www.ocpip.org.

[67]

Heiliger, H.-M., Nagel, M., Roskos, H. G., and Kurz, H. 1997. Thin-film microstrip lines for mm and sub-mm-wave on-chip interconnects. In IEEE MTT-S Int. Microwave Symp. Digest. Vol. 2. 421--424.

[68]

Ho, R., Mai, K., and Horowitz, M. 2003. Efficient on-chip global interconnects. In Symposium on VLSI Circuits. Digest of Technical Papers. IEEE, 271--274.

[69]

Ho, R., Mai, K. W., and Horowitz, M. A. 2001. The future of wires. Proceedings of the IEEE 89, 4 (April) 490--504.

[70]

Hu, J. and Marculescu, R. 2004a. Application-specific buffer space allocation for networks-on-chip router design. In ICCAD. IEEE/ACM, 354--361.

Digital Library

[71]

Hu, J. and Marculescu, R. 2004b. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 10234--10240.

Digital Library

[72]

ITRS. 2001. International technology roadmap for semiconductors. Tech. rep., International Technology Roadmap for Semiconductors.

[73]

ITRS. 2003. International technology roadmap for semiconductors. Tech. rep., International Technology Roadmap for Semiconductors.

[74]

Jalabert, A., Murali, S., Benini, L., and Micheli, G. D. 2004. XpipesCompiler: A tool for instantiating application specific networks-on-chip. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 884--889.

Digital Library

[75]

Jantsch, A. 2003. Communication performance in networks-on-chip. http://www.ele.kth.se/axel/presentations/2003/Stringent.pdf.

Digital Library

[76]

Jantsch, A. and Tenhunen, H. 2003. Networks on Chip. Kluwer Academic Publishers.

Digital Library

[77]

Jantsch, A. and Vitkowski, R. L. A. 2005. Power analysis of link level and end-to-end data protection in networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 1770--1773.

[78]

Juurlink, B. H. H. and Wijshoff, H. A. G. 1998. A quantitative comparison of parrallel computation models. ACM Trans. Comput. Syst. 16, 3 (Aug.) 271--318.

Digital Library

[79]

Kapur, P. and Saraswat, K. C. 2003. Optical interconnects for future high performance intergrated circuits. Physica E 16, 3--4, 620--627.

[80]

Karim, F., Nguyen, A., and Dey, S. 2002. An interconnect architecture for networking systems on chips. IEEE Micro 22, 36--45.

Digital Library

[81]

Karim, F., Nguyen, A., Dey, S., and Rao, R. 2001. On-chip communication architecture for OC-768 network processors. In Proceedings of the 38th Design Automation Conference (DAC). ACM, 678--683.

Digital Library

[82]

Kim, D., Lee, K., joong Lee, S., and Yoo, H.-J. 2005. A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 2369--2372.

[83]

Kim, K., Lee, S.-J., Lee, K., and Yoo, H.-J. 2005. An arbitration look-ahead scheme for reducing end-to-end latency in networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 2357--2360.

[84]

Kumar, S., Jantsch, A., Soininen, J.-P., Forsell, M., Millberg, M., Oberg, J., Tiensyrjä, K., and Hemani, A. 2002. A network-on-chip architecture and design methodology. In Proceedings of the Computer Society Annual Symposium on VLSI (ISVLSI). IEEE Computer Society, 117--124.

Digital Library

[85]

Kurd, N., Barkatullah, J., Dizon, R., Fletcher, T., and Madland, P. 2001. Multi-GHz clocking scheme for Intel pentium 4 microprocessor. In Digest of Technical Papers. International Solid-State Circuits Conference (ISSCC). IEEE, 404--405.

[86]

Lahiri, K., Raghunathan, A., and Dey, S. 2001. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures. In Proceedings of the 14th International Conference on VLSI Design. IEEE, 29--35.

Digital Library

[87]

Lahiri, K., Raghunathan, A., Lakshminarayana, G., and Dey, S. 2000. Communication architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chips. In Proceedings of the Design Automation Conference, DAC. IEEE, 513--518.

Digital Library

[88]

Lee, K. 1998. On-chip interconnects---gigahertz and beyond. Solid State Technol. 41, 9 (Sept.) 85--89.

[89]

Leiserson, C. E. 1985. Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Trans. Comput. c-34, 10, 892--901.

Digital Library

[90]

Leroy, A., Marchal, P., Shickova, A., Catthoor, F., Robert, F., and Verkest, D. 2005. Spatial division multiplexing: a novel approach for guaranteed throughput on nocs. In CODES/ISSS. ACM/IEEE, 81--86.

Digital Library

[91]

Liang, J., Laffely, A., Srinivasan, S., and Tessier, R. 2004. An architecture and compiler for scalable on-chip communication. IEEE Trans. VLSI Syst. 12, 7, 711--726.

Digital Library

[92]

Liang, J., Swaminathan, S., and Tessier, R. 2000. ASOC: A scalable, single-chip communications architecture. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. 37--46.

Digital Library

[93]

Liu, J., Zheng, L.-R., and Tenhunen, H. 2004. Interconnect intellectual property for network-on-chip (NoC). J. Syst. Archite. 50, 65--79.

Digital Library

[94]

Loghi, M., Angiolini, F., Bertozzi, D., Benini, L., and Zafalon, R. 2004. Analyzing on-chip communication in a MPSoC environment. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 752--757.

Digital Library

[95]

Madsen, J., Mahadevan, S., Virk, K., and Gonzalez, M. 2003. Network-on-chip modeling for system-level multiprocessor simulation. In Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE, 82--92.

Digital Library

[96]

Mahadevan, S., Storgaard, M., Madsen, J., and Virk, K. 2005. ARTS: A system-level framework for modeling MPSoC components and analysis of their causality. In The 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society.

Digital Library

[97]

Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W. J., and Horowitz, M. 2000. Smart memories: A modular reconfigurable architecture. In Proceedings of 27th International Symposium on Computer Architecture. 161--171.

Digital Library

[98]

Meincke, T., Hemani, A., Kumar, S., Ellervee, P., Oberg, J., Olsson, T., Nilsson, P., Lindqvist, D., and Tenhunen, H. 1999. Globally asynchronous locally synchronous architecture for large high-performance ASICs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Vol. 2. 512--515.

[99]

Millberg, M., Nilsson, E., Thid, R., and Jantsch, A. 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network-on-chip. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 890--895.

Digital Library

[100]

Mizuno, M., Dally, W. J., and Onishi, H. 2001. Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressign data. In Proceedings of the International Solid-State Circuits Conference. IEEE, 346--347, 464.

[101]

Moraes, F., Calazans, N., Mello, A., Möller, L., and Ost, L. 2004. HERMES: An infrastructure for low area overhead packet-switching networks on chip. The VLSI Integration 38, 69--93.

Digital Library

[102]

Mullins, R. and Moore, A. W. S. 2004. Low-latency virtual-channel routers for on-chip networks. In Proceedings of the 31st Annual International Symposium on Computer Architecture. IEEE, 188--197.

Digital Library

[103]

Murali, S. and Micheli, G. D. 2004a. Bandwidth-constrained mapping of cores onto noc architectures. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 20896--20902.

Digital Library

[104]

Murali, S. and Micheli, G. D. 2004b. SUNMAP: A tool for automatic topology selection and generation for NoCs. In In Proceedings of the 41st Design Automation Conference (DAC). IEEE, 914--919.

Digital Library

[105]

Muttersbach, J., Villiger, T., and Fichtner, W. 2000. Practical design of globally-asynchronous locally-synchronous systems. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society, 52--59.

Digital Library

[106]

Nakamura, K. and Horowitz, M. A. 1996. A 50&percnt; noise reduction interface using low-weight coding. In Symposium on VLSI Circuits Digest of Technical Papers. IEEE, 144--145.

[107]

Nedovic, N., Oklobdzija, V. G., and Walker, W. W. 2003. A clock skew absorbing flip-flop. In Proceedings of the International Solid-State Circuits Conference. IEEE, 342--497.

[108]

Neeb, C., Thul, M., Wehn, N., Neeb, C., Thul, M., and Wehn, N. 2005. Network-on-chip-centric approach to interleaving in high throughput channel decoders. In International Symposium on Circuits and Systems (ISCAS). IEEE, 1766--1769.

[109]

Nielsen, S. F. and Sparsø, J. 2001. Analysis of low-power SoC interconnection networks. In Proceedings of Nordchip 2001. 77--86.

[110]

Oberg, J. 2003. Clocking Strategies for Networks-on-Chip. Kluwer Academic Publishers, 153--172.

Digital Library

[111]

OCPIP. 2003a. The importance of sockets in SoC design. White paper. http://www.ocpip.org.

[112]

OCPIP. 2003b. Open Core Protocol (OCP) Specification, Release 2.0. http://www.ocpip.org.

[113]

Oklobdzija, V. G. and Sparsø, J. 2002. Future directions in clocking multi-GHz systems. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002 (ISLPED '02). ACM, 219.

Digital Library

[114]

Osso, M. D., Biccari, G., Giovannini, L., Bertozzi, D., and Benini, L. 2003. Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs. In Proceedings of 21st International Conference on Computer Design (ICCD). IEEE Computer Society, 536--539.

Digital Library

[115]

Ost, L., Mello, A., Palma, J., Moraes, F., and Calazans, N. 2005. MAIA---a framework for networks on chip generation and verification. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE.

Digital Library

[116]

Pande, P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Effect of traffic localization on energy dissipation in NoC-based interconnect. In International Symposium on Circuits and Systems (ISCAS). IEEE, 1774--1777.

[117]

Pande, P. P., Grecu, C., Ivanov, A., and Saleh, R. 2003. Design of a switch for network-on-chip applications. IEEE International Symposium on Circuits and Systems (ISCAS) 5, 217--220.

[118]

Peh, L.-S. and Dally, W. J. 1999. Flit-reservation flow control. In Proceedings of the 6th International Symposium on High-Performance Computer Architecutre (HPCA). IEEE Computer Society, 73--84.

[119]

Peh, L.-S. and Dally, W. J. 2001. A delay model for router microarchitectures. IEEE Micro 21, 26--34.

Digital Library

[120]

Pestana, S., Rijpkema, E., Radulescu, A., Goossens, K., and Gangwal, O. 2004. Cost-performance trade-offs in networks on chip: a simulation-based approach. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 764--769.

Digital Library

[121]

Philips Semiconductors. 2002. Device Transaction Level (DTL) Protocol Specification, Version 2.2.

[122]

Piguet, C., Jacques, Heer, C., O'Connor, I., and Schlichtmann, U. 2004. Extremely low-power logic. In Proceedings of Design, Automation and Testing in Europe Conference (DATE), C. Piguet, Ed. IEEE, 1530--1591.

Digital Library

[123]

Pirretti, M., Link, G., Brooks, R. R., Vijaykrishnan, N., Kandemir, M., and Irwin, M. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. 46--51.

[124]

Radulescu, A., Dielissen, J., Goossens, K., Rijpkema, E., and Wielage, P. 2004. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 878--883.

Digital Library

[125]

Rijpkema, E., Goossens, K., and Wielage, P. 2001. A router architecture for networks on silicon. In Proceeding of the 2nd Workshop on Embedded Systems. 181--188.

[126]

Rijpkema, E., Goossens, K. G. W., Radulescu, A., Dielissen, J., Meerbergen, J. V., Wielage, P., and Waterlander, E. 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks-on-chip. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 350--355.

Digital Library

[127]

Rixner, S., Dally, W. J., Kapasi, U. J., Khailany, B., LUpez-Lagunas, A., Mattson, P. R., and Owens, J. D. 1998. A bandwidth-efficient architecture for media processing. In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture. 3--13.

Digital Library

[128]

Rostislav, D., Vishnyakov, V., Friedman, E., and Ginosaur, R. 2005. An asynchronous router for multiple service levels networks on chip. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 44--53.

Digital Library

[129]

Sathe, S., Wiklund, D., and Liu, D. 2003. Design of a switching node (router) for on-chip networks. In Proceedings of the 5th International Conference on ASIC. IEEE, 75--78.

[130]

SIA. 1997. National technology roadmap for semiconductors 1997. Tech. rep., Semiconductor Industry Association.

[131]

Siguenza-Tortosa, D., Ahonen, T., and Nurmi, J. 2004. Issues in the development of a practical NoC: The Proteo concept. Integrat. VLSI J. Elsevier, 95--105.

Digital Library

[132]

Simunic, T. and Boyd, S. 2002. Managing power consumption in networks-on-chips. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE Computer Society, 110--116.

Digital Library

[133]

Singh, M. and Nowick, S. 2000. High-throughput asynchronous pipelines for fine-grain dynamic datapaths. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society, 198--209.

Digital Library

[134]

Sparsø, J. and Furber, S. 2001. Principles of Asynchronous Circuit Design. Kluwer Academic Publishers, Boston, MA.

Digital Library

[135]

Stergiou, S., Angiolini, F., Carta, S., Raffo, L., Bertozzi, D., and Micheli, G. D. 2005. Xpipes lite: A synthesis oriented design library for networks on chips. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE.

Digital Library

[136]

Svensson, C. 2001. Optimum voltage swing on on-chip and off-chip interconect. Manuscript available at http://www.ek.isy.liu.se/christer/ManuscriptSwing.pdf.

[137]

Sylvester, D. and Keutzer, K. 2000. A global wiring paradigm for deep submicron design. IEEE Trans. Comput. Aided Design Integrat. Circuits Syst. 19, 242--252.

Digital Library

[138]

SystemC. 2002. The SystemC Version 2.0.1. Web Forum (www.systemc.org).

[139]

Tamir, Y. and Frazier, G. L. 1988. High-performance multiqueue buffers for VLSI communication switches. In Proceedings of the 15th Annual International Symposium on Computer Architecture. IEEE Computer Society, 343--354.

Digital Library

[140]

Taylor, M. B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.-W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., and Agarwal, A. 2002. The RAW microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE MICRO 12, 2, 25--35.

Digital Library

[141]

Tortosa, D. A. and Nurmi, J. 2004. Packet scheduling in proteo network-on-chip. Parall. Distrib. Comput. Netw. IASTED/ACTA Press, 116--121.

[142]

Vaidya, R. S., Sivasubramaniam, A., and Das, C. R. 2001. Impact of virtual channels and adaptive routing on application performance. IEEE Trans. Parall. Distrib. Syst. 12, 2 (Feb.) 223--237.

Digital Library

[143]

Varatkar, G. and Marculescu, R. 2002. Traffic analysis for on-chip networks design of multimedia applications. In Proceedings of the 39th Design Automation Conference (DAC). ACM, 795--800.

Digital Library

[144]

VSI Alliance. 2000. Virtual component interface standard Version 2. VSI Alliance www.vsi.org.

[145]

Wang, H.-S., Zhu, X., Peh, L.-S., and Malik, S. 2002. Orion: A power-performance simulator for interconnection networks. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture. IEEE Computer Society Press, 294--305.

Digital Library

[146]

Weber, W.-D., Chou, J., Swarbrick, I., and Wingard, D. 2005. A quality-of-service mechanism for interconnection networks in system-on-chips. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 1232--1237.

Digital Library

[147]

Wieferink, A., Kogel, T., Leupers, R., Ascheid, G., Meyr, H., Braun, G., and Nohl, A. 2004. A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE Computer Society, 1256--1261.

Digital Library

[148]

Wielage, P. and Goossens, K. 2002. Networks on silicon: Blessing or nightmare? In Proceedings of the Euromicro Symposium on Digital System Design (DSD). IEEE, 196--200.

Digital Library

[149]

Worm, F., Thiran, P., Micheli, G. D., and Ienne, P. 2005. Self-calibrating networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 2361--2364.

[150]

Xanthopoulos, T., Bailey, D., Gangwar, A., Gowan, M., Jain, A., and Prewitt, B. 2001. The design and analysis of the clock distribution network for a 1.2 GHz alpha microprocessor. In Digest of Technical Papers, IEEE International Solid-State Circuits Conference, ISSCC. IEEE, 402--403.

[151]

Xu, J., Wolf, W., Henkel, J., and Chakradhar, S. 2005. A methodology for design, modeling, and analysis of networks-on-chip. In International Symposium on Circuits and Systems (ISCAS). IEEE, 1778--1781.

[152]

Xu, J., Wolf, W., Henkel, J., Chakradhar, S., and Lv, T. 2004. A case study in networks-on-chip design for embedded video. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 770--775.

Digital Library

[153]

Zhang, H., George, V., and Rabaey, J. M. 1999. Low-swing on chip signaling techniques: Effectiveness and robustness. IEEE Trans. VLSI Syst. 8, 3 (Aug.) 264--272.

Digital Library

[154]

Zhang, H., Prabhu, V., George, V., Wan, M., Benes, M., Abnous, A., and Rabaey, J. M. 2000. A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications. In International Solid-State Circuits Conference. Digest of Technical Papers (ISSCC). IEEE, 68--69.

[155]

Zimmer, H. and Jantsch, A. 2003. A fault tolerant notation and error-control scheme for switch-to-switch busses in a network-on-chip. In Proceedings of Conference on Hardware/Software Codesign and System Synthesis Conference CODES ISSS. ACM, 188--193.

Digital Library

Cited By

Singh PJung S(2025)Preamble Design and Noncoherent ToA Estimation for Pulse-Based Wireless Networks-on-Chip Communications in the Terahertz BandMicromachines10.3390/mi1601007016:1(70)Online publication date: 8-Jan-2025
https://doi.org/10.3390/mi16010070
Ma RHuang JZhang SXie YLuo G(2025)NoCFuzzer: Automating NoC Verification in UVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343019544:1(371-384)Online publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1109/TCAD.2024.3430195
Win T(2024)Enhancing Security in On-Chip Communication: A Survey of Threats and SolutionsJournal of ISMAC10.36548/jismac.2024.3.0046:3(240-253)Online publication date: Sep-2024
https://doi.org/10.36548/jismac.2024.3.004
Show More Cited By

Index Terms

A survey of research and practices of Network-on-chip

Recommendations

Using NoC routers as processing elements
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

The integration technology has increased at the point where the development of Multi-Core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, ...
Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between ...
A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures

Network-on-chip-based communication schemes represent a promising solution to the increasing complexity of system-on-chip problems. In this paper, we propose a new mesh-like topology called the shortly connected mesh technology (ScMesh), which is based ...

Comments

Information & Contributors

Information

Published In

cover image ACM Computing Surveys

ACM Computing Surveys Volume 38, Issue 1

2006

173 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/1132952

Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 June 2006

Published in CSUR Volume 38, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

853
Total Citations
View Citations
13,181
Total Downloads

Downloads (Last 12 months)350
Downloads (Last 6 weeks)27

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Singh PJung S(2025)Preamble Design and Noncoherent ToA Estimation for Pulse-Based Wireless Networks-on-Chip Communications in the Terahertz BandMicromachines10.3390/mi1601007016:1(70)Online publication date: 8-Jan-2025
https://doi.org/10.3390/mi16010070
Ma RHuang JZhang SXie YLuo G(2025)NoCFuzzer: Automating NoC Verification in UVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343019544:1(371-384)Online publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1109/TCAD.2024.3430195
Win T(2024)Enhancing Security in On-Chip Communication: A Survey of Threats and SolutionsJournal of ISMAC10.36548/jismac.2024.3.0046:3(240-253)Online publication date: Sep-2024
https://doi.org/10.36548/jismac.2024.3.004
Sukhov ARomanov ASelin M(2024)Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-ChipSymmetry10.3390/sym1601012716:1(127)Online publication date: 21-Jan-2024
https://doi.org/10.3390/sym16010127
Gonzalez-Martinez GSandoval-Arechiga RSolis-Sanchez LGarcia-Luciano LIbarra-Delgado SSolis-Escobedo JGomez-Rodriguez JRodriguez-Abdala V(2024)A Survey of MPSoC Management toward Self-AwarenessMicromachines10.3390/mi1505057715:5(577)Online publication date: 26-Apr-2024
https://doi.org/10.3390/mi15050577
Sukhov ARomanov AGlushak E(2024)Routing in circulant graphs based on a virtual coordinate systemUchenye Zapiski Kazanskogo Universiteta. Seriya Fiziko-Matematicheskie Nauki10.26907/2541-7746.2023.3.282-293165:3(282-293)Online publication date: 12-Jan-2024
https://doi.org/10.26907/2541-7746.2023.3.282-293
Weerasena HMishra P(2024)Security of Electrical, Optical, and Wireless On-chip Interconnects: A SurveyACM Transactions on Design Automation of Electronic Systems10.1145/363111729:2(1-41)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3631117
Zhang BGu HZhang GYang YMa ZSchlichtmann U(2024)A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow AccelerationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.339474735:7(1139-1154)Online publication date: Jul-2024
https://doi.org/10.1109/TPDS.2024.3394747
Tian FZhang LZhu LZhao MLiu JDong QZhao Q(2024)Advancements in Affective Disorder Detection: Using Multimodal Physiological Signals and Neuromorphic Computing Based on SNNsIEEE Transactions on Computational Social Systems10.1109/TCSS.2024.342044511:6(7309-7337)Online publication date: Dec-2024
https://doi.org/10.1109/TCSS.2024.3420445
Das APalesi MKim JPratim Pande P(2024)Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems—Overview, Challenges, and OpportunitiesIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2024.344582914:3(354-370)Online publication date: Sep-2024
https://doi.org/10.1109/JETCAS.2024.3445829
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents