article

Symmetry in temporal logic model checking

Authors:

Alastair Donaldson,

Muffy CalderAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 38, Issue 3

Pages 8 - es

https://doi.org/10.1145/1132960.1132962

Published: 30 September 2006 Publication History

Abstract

Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 38, Issue 3

2006

129 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/1132960

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