skip to main content
10.1145/1134650acmconferencesBook PagePublication PagescpsweekConference Proceedingsconference-collections
LCTES '06: Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
ACM2006 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
LCTES06: Languages, Compilers, and Tools for Embedded Systems 2006 Ottawa Ontario Canada June 14 - 16, 2006
ISBN:
978-1-59593-362-1
Published:
14 June 2006
Sponsors:
Recommend ACM DL
ALREADY A SUBSCRIBER?SIGN IN

Reflects downloads up to 08 Feb 2025Bibliometrics
Skip Abstract Section
Abstract

It is our great pleasure to welcome you to the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems -- LCTES 2006. This year's conference continues its tradition of being the premier forum for presentation of research results and experience reports on leading edge issues in embedded systems. LCTES gives researchers and practitioners a unique opportunity to share their perspectives with others interested in the various aspects of languages, compilers, and tools for embedded systems.The call for papers attracted 83 submissions from Asia-Pacific, Europe, and the Americas. Each submission was reviewed by at least 3 program committee members. The program committee meeting was held on March 25, 2006 at Columbia University, New York. The program committee accepted 21 papers that cover a variety of topics in embedded systems. We hope that the proceedings will serve as a valuable reference for researchers and developers alike.

Skip Table Of Content Section
Article
Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences

The Princeton ZebraNet project is a collaboration of engineers and biologists to build mobile, wireless embedded systems for wildlife tracking. Over the lifetime of the project, we have implemented a number of compression, communication, and data ...

SESSION: Mobile applications
Article
Feedback linking: optimizing object code layout for updates

Firmware over the air (FOTA) is becoming a standard procedure for maintaining and updating wireless embedded systems. To cope with bandwidth and storage constraints this is facilitated using incremental updates based on delta technology, i.e. only the ...

Article
Minimizing downtime in seamless migrations of mobile applications

Application migration is a key enabling technology component of mobile computing that allows rich semantics involving location awareness, trust and timeliness of information processing by moving the application where the data is. Seamlessness is one of ...

Article
Storing a persistent transactional object heap on flash memory

We present the design and implementation of TinyStore, a persistent, transactional, garbage-collected memory-management system, designed to be called from the Java virtual machine of a Java Card. The system is designed for flash-based implementations of ...

SESSION: Program analysis
Article
Deriving abstract transfer functions for analyzing embedded software

This paper addresses the problem of creating abstract transfer functions supporting dataflow analyses. Writing these functions by hand is problematic: transfer functions are difficult to understand, difficult to make precise, and difficult to debug. ...

Article
Pluggable abstract domains for analyzing embedded software

Many abstract value domains such as intervals, bitwise, constants, and value-sets have been developed to support dataflow analysis. Different domains offer alternative tradeoffs between analysis speed and precision. Furthermore, some domains are a ...

Article
Field-sensitive value analysis of embedded C programs with union types and pointer arithmetics

We propose a memory abstraction able to lift existing numerical static analyses to C programs containing union types, pointer casts, and arbitrary pointer arithmetics. Our framework is that of a combined points-to and data-value analysis. We abstract ...

SESSION: Compilation
Article
Reducing the cost of conditional transfers of control by using comparison specifications

A significant portion of a program's execution cycles are typically dedicated to performing conditional transfers of control. Much of the research on reducing the costs of these operations has focused on the branch, while the comparison has been largely ...

Article
Effective thread management on network processors with compiler analysis

Mapping packet processing tasks on network processor micro-engines involves complex tradeoffs that relating to maximizing parallelism and pipelining. Due to an increase in the size of the code store and complexity of the application requirements, ...

Article
In search of near-optimal optimization phase orderings

Phase ordering is a long standing challenge for traditional optimizing compilers. Varying the order of applying optimization phases to a program can produce different code, with potentially significant performance variation amongst them. A key insight ...

SESSION: Real-time techniques
Article
An EDF schedulability test for periodic tasks on reconfigurable hardware devices

In this paper, we consider the scheduling of periodic real-time tasks on reconfigurable hardware devices. Such devices can execute several tasks in parallel. All executing tasks share the hardware resource, which makes the scheduling problem differ from ...

Article
Faster WCET flow analysis by program slicing

Static Worst-Case Execution Time (WCET) analysis is a technique to derive upper bounds for the execution times of programs. Such bounds are crucial when designing and verifying real-time systems. WCET analysis needs a program flow analysis to derive ...

Article
Synthesizing safe state machines from Esterel

Esterel and Safe State Machines (SSMs) are synchronous languages dedicated to the modeling of embedded reactive systems. While Esterel is a textual language, SSMs are based on the graphical Statecharts formalism. Statecharts are often more intuitive to ...

SESSION: Code generation
Article
Efficient code generation from SHIM models

Programming concurrent systems is substantially more difficult than programming sequential systems, yet most embedded systems need concurrency. We believe this should be addressed through higher-level models of concurrency that eliminate many of the ...

Article
Generating optimized code from SCR specifications

A promising trend in software development is the increasing adoption of model-driven design. In this approach, a developer first constructs an abstract model of the required program behavior in a language, such as Statecharts or Stateflow, and then uses ...

Article
Effective compiler generation by architecture description

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set ...

SESSION: Low power issues
Article
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor

As the dynamic voltage scaling (DVS) technique provides system engineers the flexibility to trade-off the performance and the energy consumption, DVS has been adopted in many computing systems. However, the longer a job executes, the more energy in the ...

Article
Compiler-directed thermal management for VLIW functional units

As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached ...

Article
Bypass aware instruction scheduling for register file power reduction

Since register files suffer from some of the highest power densities within processors, designers have investigated several architectural strategies for register file power reduction, including "On Demand RF Read" where the register file is read only if ...

SESSION: Tools
Article
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures

Reconfigurable architecture is one solution to the increasing computational requirement that often cannot be met by the low-end embedded processors. Compiling applications to such architectures involves hardware/software partitioning. To partition the ...

Article
BOTS: a constraint-based component system for synthesizing scalable software systems

Embedded application developers create applications for a wide range of devices with different resource constraints. Developers want to maximize the use of the limited resources available on the device while still not exceeding the capabilities of the ...

Article
Optimizing compiler for shared-memory multiple SIMD architecture

With the rapid growth of multimedia and game, these applications put more and more pressure on the processing ability of modern processors. Multiple SIMD architecture is widely used in multimedia processing field as a multimedia accelerator.With the ...

Contributors
  • Pennsylvania State University
  • Ghent University
  1. Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems

      Recommendations

      Acceptance Rates

      Overall Acceptance Rate 116 of 438 submissions, 26%
      YearSubmittedAcceptedRate
      LCTES '14511631%
      LCTES '13601627%
      LCTES '09811822%
      LCTES '031282923%
      LCTES/SCOPES '02732534%
      LCTES '99451227%
      Overall43811626%