MTP: a Petri net-based framework for the analysis and transformation of SystemC designs

Shrinking time-to-market requires faster traversals of the design space of current complex SoC and embedded systems designs just as their complexity increases. To facilitate that designers are increasingly moving their exploration methodologies from RTL to system level. This, coupled with the need for a tighter integration between hardware and software earlier in the design cycle, has lead to emergence of mixed-level methodologies, such as SystemC, that allow for easier hardware/software codesign. In this paper, we describe a framework for the development of transformations aimed at restructuring both RTL and system-level SystemC models. We have chosen Petri nets, a well known mathematical model for concurrent systems, as our underlying formal representation. By balancing their expressive power and theoretical results transformations aimed at improving a wide range of metrics can be developed. To that effect we present the design and implementation of a semantics preserving reduction-based transformation that we have developed in previous work. Our experiments show that the resulting transformed SystemC models have indeed improved simulation performance over the original ones which often translates into designers being able to cover larger areas of the design space in the same amount of time.