article

On the construction of zero-deficiency parallel prefix circuits with minimum depth

Authors:

Chung-Kuan Cheng,

Ronald GrahamAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 2

Pages 387 - 409

https://doi.org/10.1145/1142155.1142162

Published: 01 April 2006 Publication History

Abstract

A parallel prefix circuit has n inputs x₁, x₂, …, x_n, and computes the n outputs y_i= x_i•x_i−1•…•x₁, 1 ≤i≤n, in parallel, where • is an arbitrary binary associative operator. Snir proved that the depth t and size s of any parallel prefix circuit satisfy the inequality t+s≥2n−2. Hence, a parallel prefix circuit is said to be of zero-deficiency if equality holds. In this article, we provide a different proof for Snir's theorem by capturing the structural information of zero-deficiency prefix circuits. Following our proof, we propose a new kind of zero-deficiency prefix circuit Z(d) by constructing a prefix circuit as wide as possible for a given depth d. It is proved that the Z(d) circuit has the minimal depth among all possible zero-deficiency prefix circuits.

References

[1]

Bilgory, A. and Gajski, D. D. 1986. A heuristic for suffix solutions. IEEE Trans. Comput. 35, 1 (Jan.), 34--42.

Digital Library

[2]

Brent, R. P. and Kung, H. T. 1982. A regular layout for parallel adders. IEEE Trans. Comput. 31, 3 (Mar.), 260--264.

[3]

Fich, F. E. 1983. New bounds for parallel prefix circuits. In Proceedings of the 15th Annual ACM Symposium on Theory of Computing (STOC '83). ACM, New York, 100--109.

Digital Library

[4]

Ladner, R. E. and Fischer, M. J. 1980. Parallel prefix computation. J. ACM 27, 4 (Oct.), 831--838.

Digital Library

[5]

Lakshmivarahan, S. and Dhall, S. K. 1994. Parallel Computing: Using the Prefix Problem. Oxford University Press, New York.

Digital Library

[6]

Lakshmivarahan, S., Yang, C. M., and Dhall, S. K. 1987. On a new class of optimal parallel prefix circuits with (size + depth) =2n−2 and &lceil;logn&rceil;≤depth≤(2&lceil;logn&rceil; −3). In Proceedings of the 1987 International Conference on Parallel Processing. 58--65.

[7]

Lin, Y. C. 1999. Optimal parallel prefix circuits with fan-out 2 and corresponding parallel algorithms. Neural, Parall. Sci. Comput. 7, 1 (Mar.), 33--42.

Digital Library

[8]

Lin, Y. C. and Chen, J. N. 2003. Z4: A new depth-size optimal parallel prefix circuit with small depth. Neural, Parall. Sci. Comput. 11, 3 (Sept.), 221--235.

Digital Library

[9]

Lin, Y. C. and Hsiao, J. W. 2004. A new approach to constructing optimal parallel prefix circuits with small depth. J. Parall. Distrib. Comput. 64, 1 (Jan.), 97--107.

Digital Library

[10]

Lin, Y. C., Hsu, Y. H., and Liu, C. K. 2003. Constructing h4, a fast depth-size optimal parallel prefix circuit. J. Supercomput. 24, 3 (Mar.), 279--304.

Digital Library

[11]

Lin, Y. C. and Shih, C. C. 1999. A new class of depth-size optimal parallel prefix circuits. J. Supercomput. 14, 1 (July), 39--52.

Digital Library

[12]

Sklansky, J. 1960. Conditional sum addition logic. IRE Trans. Electron. Comput. EC-9, 6 (June), 226--231.

[13]

Snir, M. 1986. Depth-size trade-offs for parallel prefix computation. J. Algor. 7, 2 (June), 185--201.

Digital Library

[14]

Zimmermann, R. Java applet for adder synthesis. In http://www.iis.ee.ethz.ch/zimmi/applets/prefix.html.

[15]

Zimmermann, R. 1996. Non-heuristic optimization and synthesis of parallel-prefix adders. In Proceedings of the International Workshop on Logic and Architecture Synthesis. 123--132.

Cited By

Lin SJiang BSheng WYoung EDe V(2024)Size-Optimized Depth-Constrained Large Parallel Prefix CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655935(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655935
Zouzias AMcColl W(2023)A Parallel Scan Algorithm in the Tensor Core Unit ModelEuro-Par 2023: Parallel Processing10.1007/978-3-031-39698-4_33(489-502)Online publication date: 28-Aug-2023
https://dl.acm.org/doi/10.1007/978-3-031-39698-4_33
Copik MGrosser THoefler TBientinesi PBerkels B(2022)Work-Stealing Prefix Scan: Addressing Load Imbalance in Large-Scale Image RegistrationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.309523033:3(523-535)Online publication date: 1-Mar-2022
https://dl.acm.org/doi/10.1109/TPDS.2021.3095230
Show More Cited By

Index Terms

On the construction of zero-deficiency parallel prefix circuits with minimum depth
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

Constructing zero-deficiency parallel prefix adder of minimum depth
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as S_C(n) and d_C(n) respectively. Snir proved that s_C(n) + d_C(n) ≥ 2n - 2 holds for arbitrary ...
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2

Prefix computation is used in various areas and is considered as a primitive operation. Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. The depth of a prefix circuit is a measure of its processing time; ...
Faster optimal parallel prefix circuits: New algorithmic construction

Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. A prefix circuit with n inputs is depth-size optimal if its depth plus size equals 2n-2. Smaller depth implies faster computation, while smaller size implies ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 2

April 2006

283 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1142155

Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2006

Published in TODAES Volume 11, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

19
Total Citations
View Citations
284
Total Downloads

Downloads (Last 12 months)10
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Lin SJiang BSheng WYoung EDe V(2024)Size-Optimized Depth-Constrained Large Parallel Prefix CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655935(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655935
Zouzias AMcColl W(2023)A Parallel Scan Algorithm in the Tensor Core Unit ModelEuro-Par 2023: Parallel Processing10.1007/978-3-031-39698-4_33(489-502)Online publication date: 28-Aug-2023
https://dl.acm.org/doi/10.1007/978-3-031-39698-4_33
Copik MGrosser THoefler TBientinesi PBerkels B(2022)Work-Stealing Prefix Scan: Addressing Load Imbalance in Large-Scale Image RegistrationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.309523033:3(523-535)Online publication date: 1-Mar-2022
https://dl.acm.org/doi/10.1109/TPDS.2021.3095230
Liao QLi S(2020)A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low AreaProceedings of the 2020 4th International Conference on Digital Signal Processing10.1145/3408127.3408185(284-288)Online publication date: 19-Jun-2020
https://dl.acm.org/doi/10.1145/3408127.3408185
El-Boghdadi H(2015)Dynamic-width reconfigurable parallel prefix circuitsThe Journal of Supercomputing10.1007/s11227-014-1270-271:4(1177-1195)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s11227-014-1270-2
El-Boghdadi H(2013)Dynamic-Width Reconfigurable Parallel Prefix CircuitsProceedings of the 2013 IEEE 16th International Conference on Computational Science and Engineering10.1109/CSE.2013.27(109-116)Online publication date: 3-Dec-2013
https://dl.acm.org/doi/10.1109/CSE.2013.27
El-Boghdadi H(2013)A class of almost-optimal size-independent parallel prefix circuitsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2013.03.01273:6(888-894)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jpdc.2013.03.012
El-Boghdadi H(2012)A Class of an Almost-Optimal Size-Independent Parallel Prefix CircuitsProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum10.1109/IPDPSW.2012.225(1820-1826)Online publication date: 21-May-2012
https://dl.acm.org/doi/10.1109/IPDPSW.2012.225
Lin YKo C(2011)New Parallel Prefix Algorithm for MulticomputersProceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications10.1109/ISPA.2011.10(7-12)Online publication date: 26-May-2011
https://dl.acm.org/doi/10.1109/ISPA.2011.10
Sheeran M(2011)Functional and dynamic programming in the design of parallel prefix networksJournal of Functional Programming10.1017/S095679681000030421:1(59-114)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1017/S0956796810000304
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents