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On the construction of zero-deficiency parallel prefix circuits with minimum depth

Published: 01 April 2006 Publication History

Abstract

A parallel prefix circuit has n inputs x1, x2, …, xn, and computes the n outputs yi= xixi−1•…•x1, 1 ≤in, in parallel, where • is an arbitrary binary associative operator. Snir proved that the depth t and size s of any parallel prefix circuit satisfy the inequality t+s≥2n−2. Hence, a parallel prefix circuit is said to be of zero-deficiency if equality holds. In this article, we provide a different proof for Snir's theorem by capturing the structural information of zero-deficiency prefix circuits. Following our proof, we propose a new kind of zero-deficiency prefix circuit Z(d) by constructing a prefix circuit as wide as possible for a given depth d. It is proved that the Z(d) circuit has the minimal depth among all possible zero-deficiency prefix circuits.

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  • (2024)Size-Optimized Depth-Constrained Large Parallel Prefix CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655935(1-6)Online publication date: 23-Jun-2024
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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 11, Issue 2
    April 2006
    283 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1142155
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 April 2006
    Published in TODAES Volume 11, Issue 2

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    Author Tags

    1. Zero-deficiency
    2. depth-size trade-off
    3. parallel prefix circuits

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    View all
    • (2024)Size-Optimized Depth-Constrained Large Parallel Prefix CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655935(1-6)Online publication date: 23-Jun-2024
    • (2023)A Parallel Scan Algorithm in the Tensor Core Unit ModelEuro-Par 2023: Parallel Processing10.1007/978-3-031-39698-4_33(489-502)Online publication date: 28-Aug-2023
    • (2022)Work-Stealing Prefix Scan: Addressing Load Imbalance in Large-Scale Image RegistrationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.309523033:3(523-535)Online publication date: 1-Mar-2022
    • (2020)A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low AreaProceedings of the 2020 4th International Conference on Digital Signal Processing10.1145/3408127.3408185(284-288)Online publication date: 19-Jun-2020
    • (2015)Dynamic-width reconfigurable parallel prefix circuitsThe Journal of Supercomputing10.1007/s11227-014-1270-271:4(1177-1195)Online publication date: 1-Apr-2015
    • (2013)Dynamic-Width Reconfigurable Parallel Prefix CircuitsProceedings of the 2013 IEEE 16th International Conference on Computational Science and Engineering10.1109/CSE.2013.27(109-116)Online publication date: 3-Dec-2013
    • (2013)A class of almost-optimal size-independent parallel prefix circuitsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2013.03.01273:6(888-894)Online publication date: 1-Jun-2013
    • (2012)A Class of an Almost-Optimal Size-Independent Parallel Prefix CircuitsProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum10.1109/IPDPSW.2012.225(1820-1826)Online publication date: 21-May-2012
    • (2011)New Parallel Prefix Algorithm for MulticomputersProceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications10.1109/ISPA.2011.10(7-12)Online publication date: 26-May-2011
    • (2011)Functional and dynamic programming in the design of parallel prefix networksJournal of Functional Programming10.1017/S095679681000030421:1(59-114)Online publication date: 1-Jan-2011
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