Radu Marculescu
Skip Abstract Section
Abstract
Continuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic manner. Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis. In addition, a communication refinement step is critical for optimizing the communication infrastructure in this multiprocessor setup. Finally, simulation and prototyping can be used for accurate performance evaluation purposes.
- Adriahantenaina, A. and Greiner, A. 2003. Micro-network for SoC: Implementation of a 32-Port SPIN network. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Ascia, G., Catania, V., and Palesi, M. 2004. Multi-objective mapping for mesh-based NoC architectures. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis. Google Scholar
- Bailey, N. 1975. The Mathematical Theory of Infectious Diseases, 2nd ed. Charles Griffin, London.Google Scholar
- Balarin, F., Watanabe, Y., Hsieh, H., Lavagno, L., Passerone, C., and Sangiovanni-Vincentelli, A. 2003. Metropolis: An integrated electronic system design environment. IEEE Computer 36, 4, 45--52. Google Scholar
- Bartic, T. A., Mignolet, J.-Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., and Lauwereins, R. 2003. Highly scalable network on chip for reconfigurable systems. In Proceedings of the International Symposium on System-on-Chip.Google Scholar
- Benini, L. and De Micheli, G. 2002. Networks on chips: A new SoC paradigm. IEEE Comput. 35, 1. Google Scholar
- Beran, J. 1994. Statistics for Long-Memory Processes. Chapman & Hall, London.Google Scholar
- Bergstra, J. A. and Klop, J. W. 1985. Algebra of communicating processes with abstraction. Theoretical Comput. Sci. 37, 1.Google Scholar
- Bertozzi, D., Benini, L., and De Micheli, G. 2002. Low power error resilient encoding for on-chip data buses. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Bertsekas, D. and Gallager, R. 1987. Data Networks. Prentice-Hall, Upper Saddle River, N.J. Google Scholar
- Carloni, L. P. and Sangiovanni-Vincentelli, A. L. 2002. Coping with latency in SoC design. IEEE Micro (Special Issue on System on Chip) 22, 5. Google Scholar
- Chandra, V., Xu, A., Schmit, H., and Pileggi, L. 2004. An interconnect channel design for high performance integrated circuits. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Chiu, G.-M. 2000. The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distributed Syst. 11, 7, 729--738. Google Scholar
- Constantinescu, C. 2001. Dependability analysis of a fault-tolerant processor. In Proceedings of the Pacific Rim International Symposium on Dependable Computing. Google Scholar
- Constantinescu, C. 2002. Impact of deep submicron technology on dependability of VLSI circuits. In Proceedings of the International Conference on Dependable Systems and Networks. Google Scholar
- Dally, W. and Towles, B. 2001. Route packets, not wires: On-Chip interconnection networks. In Proceedings of the 38th ACM IEEE Design Automation Canference. Google Scholar
- Duato, J., Yalamanchili, S., and Ni, L. M. 2002. Interconnection Networks: An Engineering Approach. Morgan Kaufmann, San Fransisco, Calif. Google Scholar
- Dumitras, T. and Marculescu, R. 2003. On-Chip stochastic communication. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Ferrari, A. and Sangiovanni-Vincentelli, A. 1999. System design: Traditional concepts and new paradigms. In Proceedings of the International Conference on Computer Design. Google Scholar
- Flynn, D. 1997. AMBA: Enabling reusable on-chip designs. IEEE Micro 17, 4, 20--27. Google Scholar
- Geilen, M. C. W., Basten, T., and Stuijk, S. 2005. Minimising buffer requirements of synchronous dataflow graphs with model checking. In Proceedings of the ACM IEEE Design Automation Conference. Google Scholar
- Glass, C. J. and Ni, L. M. 1992. The turn model for adaptive routing. J. ACM 41, 5, 874--902. Google Scholar
- Gotz, N., Herzog, U., and Rettelbach, M. 1993. Multiprocessor and distributed system design: The integration of functional specification and performance analysis using stochastic process algebras. In Tutorial Proceedings of the 16th International Symposium on Computer Performance Modelling, Measurement and Evaluation, vol. 729. Lecture Notes in Computer Science, Springer Verlag, New York. Google Scholar
- Hedetniemi, S. M., Hedetniemi, S. T., and Liestman, A. L. 1988. A survey of gossiping and broadcasting in communication networks. Networks 18, 4, 319--359.Google Scholar
- Hemani, A., Jantsch, A., Kumar, S., Postula, A., Oberg, J., Millberg, M., and Lindqvist, D. 2000. Network on a chip: An architecture for billion transistor era. In Proceedings of the IEEE NorChip Conference.Google Scholar
- Hillstone, J. 1996. A Compositional Approach to Performance Modelling. Cambridge University Press, Cambridge Mass. Google Scholar
- Horst, R., Jewett, D., and Lenowski, D. 1993. The risk of data corruption in microprocessor based systems. In Proceedings of the 23rd International Symposium on Fault-Tolerant Computing.Google Scholar
- Hu, J. and Marculescu, R. 2004. DyAD-Smart routing for networks-on-chip. In Proceedings of the Design Automation Conference. Google Scholar
- Hu, J. and Marculescu, R. 2004a. Application-specific buffer space allocation for Networks-on-Chip router design. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA. Google Scholar
- Hu, J. and Marculescu, R. 2005a. Communication and task scheduling of application-specific Networks-on-chip. IEE Proceedings Comput. Digital Techniques. 152, 5, 643--651.Google Scholar
- Hu, J. and Marculescu, R. 2005b. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 24, 4. Google Scholar
- Hu, J., Ogras, U. Y., and Marculescu, R. System-level buffer allocation for application-specific Networks-on-Chip router design. IEEE Trans Comput. Aided Des. Integrated Circuits Syst. To appear. Google Scholar
- Hung, W., Addo-Quaye, C., Theocharides, T., Xie, Y., Vijakrishnan, N., and Irwin, M. J. 2004. Thermal-aware IP virtualization and placement for networks-on-chip architecture. In Proceedings of the IEEE Conference on Computer Design. Google Scholar
- IBM CoreConnect. 2006. http://www.chips.ibm.com/products/powerpc/cores.Google Scholar
- Jalabert, A., Murali, S., Benini, L., and De Micheli, G. 2004. × pipesCompiler: A tool for instantiating application specific networks on chip. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Jantsch, A. and Tenhunen, H. (Eds.). 2003. Networks-on-Chip. Kluwer, Hingham, Mass. Google Scholar
- Kahn, G.1974. The semantics of a simple language for parallel programming. In Information Processing, J. L. Rosenfeld, ed. Stockholm, Sweden.Google Scholar
- Kim, J. and Shin, K. G. 1996. Execution time analysis of communicating tasks in distributed systems. IEEE Trans. Comput. 45, 5, 572--579. Google Scholar
- Lee, E. and Messerschmitt, D. 1987. Synchronous dataflow. In Proc. IEEE 75, 9, 1235--1245.Google Scholar
- Lee, E. and Parks, T. M. 1995. Dataflow process networks. Proc. IEEE 83, 5.Google Scholar
- Lee, H. G., Ogras, U. Y., Marculescu, R., and Chang, N. 2006. Design space exploration and prototyping for on-chip multimedia applications. In Proceedings of the Design Automation Conference. Google Scholar
- Lieverse, P., Wolf, P., Vissers, K., and Deprettere, E. 2001. A methodology for architecture exploration of heterogeneous signal processing systems. J. VLSI Signal Processing Syst. Signal, Image Video Technol. 29, 3. Google Scholar
- Lin, T. and Pileggi, L. T. 2002. Throughput-Driven IC communication fabric synthesis. In Proceedings of the International Conference on Computer-Aided Design. Google Scholar
- Maly, W. 2001. IC design in high-cost nanometer technologies era. In Proceedings of the 38th Conference on Design Automation. Google Scholar
- Manolache, S., Eles, P., and Peng, Z. 2005. Fault and Energy aware communication mapping with quaranteed latency for applications implemented on NoC. In Proceedings of the Design Automation Conference. Google Scholar
- Marculescu, R., Nandi, A., Lavagno, L., and Sangiovanni-Vincentelli, A. 2001. System-Level power/performance analysis of portable multimedia systems communicating over wireless channels. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design. Google Scholar
- Maxiaguine, A., Kuenzli, S., Chakraborty S., and Thiele, L. 2004. Rate analysis for streaming applications with on-chip buffer constraints. In Proceedings of the Asia and South Pacific Design Automation Conference. Google Scholar
- Milner, R. 1989. Communication and Concurrency. Prentice-Hall, Englewood Cliffs, N.J. Google Scholar
- Mishra, P. Shrivastava, A., and Dutt, N. Architecture description language (ADL-) Driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Elect. Syst. 11, 3, 626--658. Google Scholar
- Morgenstein, A. 2004. Comparative analysis of serial vs. parallel links in networks on chip. In Proceedings of the International Symposium on Systems on Chip.Google Scholar
- Murali, S. and De Micheli, G. 2004a. Bandwidth-Constrained mapping of cores onto NoC architectures. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Murali, S. and De Micheli, G. 2004b. SUNMAP: A tool for automatic topology selection and generation for NoCs. In Proceedings of the Design Automation Conference. Google Scholar
- Nandi, A. and Marculescu, R. 2001. System-Level power/performance analysis for embedded systems design. In Proceedings of the 38th ACM/IEEE Design Automation Conference. Google Scholar
- Ni, L. M. and McKinley, P. K. 1993. A survey of wormhole routing techniques in direct networks. IEEE Trans. Comput. 26. Google Scholar
- Norros, I. 1994. A storage model with self-similar input. Queueing Syst. 16, 3--4, 387--396.Google Scholar
- Ogras, U. Y., Hu, J., and Marculescu, R. 2005. Key research problems in NoC design: A holistic perspective. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthses. Google Scholar
- Ogras, U. Y. and Marculescu, R. 2005a. Application-Specific network-on-chip architecture customization via long-range link insertion. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Google Scholar
- Ogras, U. Y. and Marculescu, R. 2005b. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Ogras, U. Y., Marculescu, R., Lee, H. G., and Chang, N. 2006. Communication architecture optimization: Making the shortest path shorter in regular networks-on-chip. In Proceedings of the Design Automation and Test in Europe Conference. Google Scholar
- Ogras, U. Y. and Marculescu, R. 2006a. It's a small world after all; NoC performance optimization via long link insertion. IEEE Trans. Very Large Scale Integrat. Syst. (Special Section Hardware/ Software Codesign and System Synthesis.) Google Scholar
- Open Core Protocol International Partnership (OCP-IP).2006. OCP datasheet. http://www. ocpip.org.Google Scholar
- Peterson, J. L. 1981. Petri Net Theory and the Modeling of Systems. Prentice-Hall, Englewood Cliffs, N.J. Google Scholar
- Pinto, A. and Sangiovanni-Vincentelli, A. 2003. Efficient synthesis of networks on chip. In Proceedings of the 21st International Conference on Computer Designe. Google Scholar
- Pinto, A., Bonivento, A., Sangiovanni-Vincentelli, A. L., Passerone, R., and Sgroi, M. 2006. System level design paradigms: Platform-based design and communication synthesis. ACM Trans. Design Autom. Elect. Syst., 11, 3, 537--563. Google Scholar
- Pirretti, M. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI.Google Scholar
- Plateau, B. and Atif, K. 1991. Stochastic automata network for modeling parallel systems. IEEE Trans. Softw. Eng. 17, (Oct.). Google Scholar
- Plateau, B. and Fourneau, J. M. 1991. A methodology for solving Markov models of parallel systems. J. Parallel Distrib. Comput. 12, 4, 370--387. Google Scholar
- Pop, P. and Eles, P. 2006. Analysis and optimization of communication-dominated real-time embedded systems. ACM Trans. Design Autom. Elect. Syst. 11, 3, 593--625. Google Scholar
- Saastamoinen, I., Alho, M., and Nurmi, J. 2003. Buffer implementation for proteo network-on-chip. In Proceedings of the International Symposium on Circuits and Systems.Google Scholar
- Semiconductor Association. 2003. The International Technology Roadmap for Semiconductors (ITRS).Google Scholar
- Shang, L., Peh, L. S., and Jha, N. K. 2006. POWERHERD: A distributed scheme for dynamic satisfying peak power constraints in interconnection networks. IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 25, 1, 92--110. Google Scholar
- Srinivasan, K., Chatha, K. S., and Konjevod, G. 2004. Linear programming based techniques for synthesis of network-on-chip architectures. In Proceedings of the IEEE International Conference on Computer Design. Google Scholar
- Sriram, S. and Bhattacharyya, S. S. 2001. Embedded Multiprocessors Scheduling and Synchronization. Marcel Dekker, New York. Google Scholar
- Stewart, W. 1994. An Introduction to the Numerical Solution of Markov Chains. Princeton University Press, N.J.Google Scholar
- Stewart, W., Atif, K., and Plateau, B. 1995. The numerical solution of stochastic automata networks. In European J. Operational Research 86, 503--525.Google Scholar
- Trivedi, K. S. 1982.Probability and Statistics with Reliability, Queueing, and Computer Science Applications. Prentice-Hall., Englewood Cliffs, N.J. Google Scholar
- Varatkar, G. and Marculescu, R. 2004. On-Chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans. VLSI 12, 1, 108--119. Google Scholar
- Yang, G., Sangiovanni-Vincentelli, A., Watanabe, Y., and Balarin, F. 2004. Separation of concerns: Overhead in modeling and efficient simulation techniques. In Proceedings of the ACM 4th International Conference on Embedded Software. Google Scholar
- Ye, T. T., Benini, L., and De Micheli, G. 2002. Analysis of power consumption on switch fabrics in network routers. In Proceedings of the Design Automation Conference. Google Scholar
- Ye, T. T. and De Micheli, G. 2003. Physical planning for multiprocessor networks and switch fabrics. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors.Google Scholar
Index Terms
- Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Recommendations
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
DAC '04: Proceedings of the 41st annual Design Automation ConferenceContinuous advancements in semiconductor technology enable the design of complex systems-on-chips (SoCs) composed of tens or hundreds of IP cores. At the same time, the applications that need to run on such platforms have become increasingly complex and ...
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system designNetworks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in Systems-on-Chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose ...
Design automation for application-specific on-chip interconnects
On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-Chip, particularly in data-intensive applications, where the choice of the underlying communication architecture, tailored on the particular application ...
Comments