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A reconfigurable design-for-debug infrastructure for SoCs

Published: 24 July 2006 Publication History

Abstract

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

References

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A. Berent. Debugging Techniques for Embedded Systems using Real-Time Software Trace. http://www.arm.com/pdfs/CoresightWhitepaper.pdf
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J. Bower, O. Mencer, W. Luck, and M. Abramovici. An SoC with Reconfigurable Debug Infrastructure. Proceedings of COOL Chips IX Conf., April 2006
[3]
Collett ASIC/IC Verification Study, 2004 (data for 180nm and 130nm)
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Jiang, W., T. Marwah and D. Bouldin. Enhancing Reliability and Flexibility of a System-on-Chip Using Reconfigurable Logic. Proc. of the Midwest Symp. on Circuits and Systems, Aug. 2005.
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Y. Hsu, B. Tabbara, Y. Chen, and F. Tsai. Advanced Techniques for RTL Debugging. Proc 40th Design Automation Conf., June, 2003.
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Y.Hsu. Visibility Enhancement for Silicon Debug. Proc. 43rd Design Automation Conf., July, 2006.
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N. Kafafi, K. Bozman, and S.J.E. Wilton. Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores. Proc. ACM/SIGDA Intn'l. Symp. on FPGAs, Febr. 2003
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R. Leatherman, B. Ableidinger, and N. Stollon. Processor and System Bus On-Chip Instrumentation. Proc. Embedded Systems Conference, April 2003.
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N. Kafafi, K. Bozman, and S.J.E. Wilton. Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores. Proc. ACM/SIGDA Intn'l. Symp. on FPGAs, Febr. 2003
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B. Vermeulen and S.K. Goel. Design for Debug: Catching Design Errors in Digital Chips. IEEE Design & Test of Computers, May/June 2002
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http://www.accellera.org/activities/ovl/

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  • (2023)Post Silicon Validation for I2C (SMBUS) Peripheral2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00070(313-318)Online publication date: Jan-2023
  • (2023)ML-Based Online Design Error Localization for RISC-V Implementations2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224864(1-7)Online publication date: 3-Jul-2023
  • (2023)Conventional Methods for Fault DiagnosisMachine Learning Support for Fault Diagnosis of System-on-Chip10.1007/978-3-031-19639-3_2(25-57)Online publication date: 14-Mar-2023
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  1. A reconfigurable design-for-debug infrastructure for SoCs

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      cover image ACM Conferences
      DAC '06: Proceedings of the 43rd annual Design Automation Conference
      July 2006
      1166 pages
      ISBN:1595933816
      DOI:10.1145/1146909
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 24 July 2006

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      Author Tags

      1. assertion-based debug
      2. at-speed debug
      3. silicon debug
      4. what-if experiments

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      DAC06: The 43rd Annual Design Automation Conference 2006
      July 24 - 28, 2006
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      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      • (2023)Post Silicon Validation for I2C (SMBUS) Peripheral2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)10.1109/VLSID57277.2023.00070(313-318)Online publication date: Jan-2023
      • (2023)ML-Based Online Design Error Localization for RISC-V Implementations2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS59296.2023.10224864(1-7)Online publication date: 3-Jul-2023
      • (2023)Conventional Methods for Fault DiagnosisMachine Learning Support for Fault Diagnosis of System-on-Chip10.1007/978-3-031-19639-3_2(25-57)Online publication date: 14-Mar-2023
      • (2022)A Proposition to Effective Execution of Power-On Test Case Script over SoC under Post-Silicon-Validation2022 IEEE 6th Conference on Information and Communication Technology (CICT)10.1109/CICT56698.2022.9997869(1-5)Online publication date: 18-Nov-2022
      • (2022)A Secure JTAG Wrapper for SoC Testing and DebuggingIEEE Access10.1109/ACCESS.2022.316471210(37603-37612)Online publication date: 2022
      • (2021)PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST52088.2021.9493373(1-6)Online publication date: 5-Jul-2021
      • (2021)FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT52944.2021.9568317(1-6)Online publication date: 6-Oct-2021
      • (2021)A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and KeyIEEE Access10.1109/ACCESS.2021.30973489(102161-102176)Online publication date: 2021
      • (2021)On-Chip Error Detection Reusing Built-In Self-Repair for Silicon DebugIEEE Access10.1109/ACCESS.2021.30715179(56443-56456)Online publication date: 2021
      • (2020)Method for Testing and Debugging Flow Formal Specification in Full-Stack Embedded Systems Designs2020 9th Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO49872.2020.9134213(1-4)Online publication date: Jun-2020
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