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Hierarchical bottom-up analog optimization methodology validated by a delta--sigma A/D converter design for the 802.11a/b/g standard

Published: 24 July 2006 Publication History

Abstract

This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for WLAN applications, to generate a set of Pareto--optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto--optimal performance solutions of the hierarchical lower--level sub--blocks to generate the overall Pareto--optimal set at system level. The way the lower--level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom--up methodology. The experimental results validate the methodology for a 7--block hierarchical decomposition of a complex high--speed ΔΣ A/D modulator for a WLAN 802.11a/b/g standard.

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  • (2017)New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD.2017.7981582(1-4)Online publication date: Jun-2017
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  • (2009)Using Pareto-Optimal Fronts in the Design of Reconfigurable Data ConvertersProceedings of the 2009 Second International Conference on Advances in Circuits, Electronics and Micro-electronics10.1109/CENICS.2009.20(34-39)Online publication date: 11-Oct-2009
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cover image ACM Conferences
DAC '06: Proceedings of the 43rd annual Design Automation Conference
July 2006
1166 pages
ISBN:1595933816
DOI:10.1145/1146909
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 July 2006

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  1. hierarchical synthesis

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July 24 - 28, 2006
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Cited By

View all
  • (2017)New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD.2017.7981582(1-4)Online publication date: Jun-2017
  • (2011)Hierarchical synthesis system with hybrid DLO‐MOGA optimizationCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/0332164111110118630:2(741-761)Online publication date: 8-Mar-2011
  • (2009)Using Pareto-Optimal Fronts in the Design of Reconfigurable Data ConvertersProceedings of the 2009 Second International Conference on Advances in Circuits, Electronics and Micro-electronics10.1109/CENICS.2009.20(34-39)Online publication date: 11-Oct-2009
  • (2009)ANTIGONEIntegration, the VLSI Journal10.1016/j.vlsi.2008.07.00142:1(10-23)Online publication date: 1-Jan-2009
  • (2008)Yield-aware hierarchical optimization of large analog integrated circuitsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509485(79-84)Online publication date: 10-Nov-2008
  • (2008)Fuzzy techniques in optimizationProceedings of the 9th WSEAS International Conference on Fuzzy Systems10.5555/1416056.1416085(178-191)Online publication date: 2-May-2008
  • (2008)A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodologyAnalog Integrated Circuits and Signal Processing10.1007/s10470-008-9148-y55:1(37-45)Online publication date: 1-Apr-2008
  • (2008)Analog and Mixed-Signal Design StrategiesHigh-Level Modeling and Synthesis of Analog Integrated Systems10.1007/978-1-4020-6802-7_3(37-81)Online publication date: 2008
  • (2007)Yield-aware analog integrated circuit optimization using geostatistics motivated performance modelingProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326169(464-469)Online publication date: 5-Nov-2007
  • (2007)An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selectionProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266386(81-86)Online publication date: 16-Apr-2007
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