Cited By
View all- Keller BChakravadhanula K(2009)Test Strategies for Gated Clock DesignsPower-Aware Testing and Test Strategies for Low Power Devices10.1007/978-1-4419-0928-2_9(273-293)Online publication date: 13-Aug-2009
- Huang YLin X(2007)Programmable Logic BIST for At-speed Test16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.83(295-300)Online publication date: Oct-2007