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A flexible and scalable methodology for GHz-speed structural test

Published: 24 July 2006 Publication History

Abstract

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Simulation-based functional test is difficult because low-cost testers are unable to supply multiple asynchronous clocks to the IC. Moreover, low-cost testers simply cannot operate at chip speed. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for GHz-speed structural test of ASICs having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We also describe a method to test asynchronous clock domains simultaneously. Experimental results for two multi-million gate ASICs demonstrate high at-speed coverage.

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Cited By

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  • (2009)Test Strategies for Gated Clock DesignsPower-Aware Testing and Test Strategies for Low Power Devices10.1007/978-1-4419-0928-2_9(273-293)Online publication date: 13-Aug-2009
  • (2007)Programmable Logic BIST for At-speed Test16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.83(295-300)Online publication date: Oct-2007

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  1. A flexible and scalable methodology for GHz-speed structural test

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      cover image ACM Conferences
      DAC '06: Proceedings of the 43rd annual Design Automation Conference
      July 2006
      1166 pages
      ISBN:1595933816
      DOI:10.1145/1146909
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 24 July 2006

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      Author Tags

      1. ASICs
      2. asynchronous clock domains
      3. at-speed
      4. deskewer
      5. structural test
      6. test waveform generator

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      July 24 - 28, 2006
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      Cited By

      View all
      • (2009)Test Strategies for Gated Clock DesignsPower-Aware Testing and Test Strategies for Low Power Devices10.1007/978-1-4419-0928-2_9(273-293)Online publication date: 13-Aug-2009
      • (2007)Programmable Logic BIST for At-speed Test16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.83(295-300)Online publication date: Oct-2007

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