ABSTRACT
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new ar-chitecture-aware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our approach, CAPRI, can be viewed as an embedding of a graph representing the netlist into a metric space that is representative of the FPGA. First, we develop an analytic metric of distance that models delays along the FPGA routing grid. We then embed a netlist into the defined metric space using matrix projections and online bipartite matching. Experimental comparisons with the popular FPGA tool, VPR, show that with CAPRI's initial solution, the resulting placements show median improvements of 10% in critical path delays for the larger MCNC benchmarks. Total placement runtime is also improved by 2x on average.
- D. P. Bertsekas. Nonlinear Programming. Athena, 1999.Google Scholar
- J. P. Blanks. Near-optimal placement using a quadratic objective function. In DAC, 1985. Google ScholarDigital Library
- H. Eisenmann and F. M. Johannes. Generic global placement and oorplanning. In DAC, 1998. Google ScholarDigital Library
- J. Frankle and R. M. Karp. Circuit placements and cost bounds by eigenvector decomposition. In ICCAD, 1986.Google Scholar
- G. Parthasarathy, et al. Interconnect complexity-aware FPGA placement using Rent's rule. In SLIP, 2001. Google ScholarDigital Library
- G.Chen and J.Cong. Simultaneous Timing Driven Clustering and Placement for FPGAs. In FPL, 2004.Google ScholarCross Ref
- G.H.Golub and C. Loan. Matrix Computations. JHU, 1983.Google Scholar
- T. F. Gonzalez. Clustering to minimize the maximum intercluster distance. Theoretical Comp. Sci., 38, 1985.Google Scholar
- D. Harel and Y. Koren. Graph Drawing by High Dimensional Embedding. In Graph Drawing, 2002. Google ScholarDigital Library
- M. Khellah, S.Brown, and Z.Vranesic. Modeling routing delays in SRAM-based FPGAs. In Canadian Conf. on VLSI, 1993.Google Scholar
- A. Marquardt, V. Betz, and J. Rose. Timing-Driven Placement for FPGAs. In FPGA, 2000. Google ScholarDigital Library
- J. Matousek. Lectures in Discrete Geometry. Springer, 2002. Google ScholarDigital Library
- M.Hutton, et al. Timing Driven Placement for Hierarchical Programmable Logic Devices. In FPGA, 2001. Google ScholarDigital Library
- N.Selvakkumaran, et al. Partitioning Algorithms for FPGAs with Heterogeneous Resources. In FPGA, 2004. Google ScholarDigital Library
- P.Maidee, et al. Fast Timing-driven Partitioning-based Placement for Island-style FPGAs. In DAC, 2003. Google ScholarDigital Library
- R.A.Finkel and J.L.Bentley. Quad Trees: A Data Structure for Retrieval of Composite Keys. Acta Informatica, 4(1), 1974.Google Scholar
- R.Jayaraman. Physical Design for FPGAs. In ISPD, 2001. Google ScholarDigital Library
- S.K.Nag and R.Rutenbar. Performance-driven Simultaneous Placement and Routing for FPGAs. IEEE TCAD, 17(6), 1998. Google ScholarDigital Library
- S.Sahni and T.Gonzalez. P-complete approximation problems. Journal of ACM, 23, 1976. Google ScholarDigital Library
- T.H.Cormen, C.E.Leiserson, and R.L.Rivest. Introduction to Algorithms. MIT Press, 1995. Google ScholarDigital Library
- T.Karnik and S-M.Kang. An Empirical Model for Estimation of Routing Delays in FPGAs. In ICCAD, 1995. Google ScholarDigital Library
- T.Taghavi, S.Ghiasi, A.Ranjan, S.Raje, and M.Sarrafzadeh. Innovate or Perish: FPGA Physical Design. In ISPD, 2004. Google ScholarDigital Library
- www.altera.com.Google Scholar
- www.eecg.toronto.edu/evaughn/challenge/challenge.html.Google Scholar
- www.xilinx.com.Google Scholar
- Y.Chang, et al. An architecture-driven metric for simultaneous placement and global routing for FPGAs. In DAC, 2000. Google ScholarDigital Library
Index Terms
- Architecture-aware FPGA placement using metric embedding
Recommendations
Routing-architecture-aware analytical placement for heterogeneous FPGAs
DAC '15: Proceedings of the 52nd Annual Design Automation ConferencePlacement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed ...
Routability-Driven Blockage-Aware Macro Placement
DAC '14: Proceedings of the 51st Annual Design Automation ConferenceWe present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CP-trees can flexibly pack movable macros toward corners or pre-placed macros along chip boundaries circularly to optimize macro ...
Clock-Aware FPGA Placement Contest
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical DesignModern FPGA device contains complex clocking architecture on top of FPGA logic fabric. To best utilize FPGA clocking architecture, both FPGA designers and EDA tool developers need to understand the clocking architecture and design best methodology/...
Comments