skip to main content
10.1145/1146909.1147139acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

GreenBus: a generic interconnect fabric for transaction level modelling

Published: 24 July 2006 Publication History

Abstract

In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface API's that are required in order to model those (and we believe other) busses and IO structures. Third the surrounding infrastructure that we believe can, and should be in place to support the modelling of those busses and IO structures. We will present the infrastructure that we have built, and indicate where our future work will hea.

References

[1]
Intel Corp. Aztalan TLM bus infrastructure. Intel Corp., 2005.
[2]
IBM. IBM PowerPC 405 Evaluation Kit with CoreConnect SystemC TLMs. IBM Corp., 2006. http://www.ibm.com
[3]
A. Donlin and M. Burton. Transaction Level Modeling : Above RTL design and methodology. internal OSCI TLM WG document, February 2004.
[4]
A. Gerstlauer, D. Shin, R. Doemer, and D. Gajski. System-Level Communication Modeling for Network-on-Chip Synthesis. ASP-DAC, 2005.
[5]
F. Ghenassia. Transaction-Level Modeling with SystemC : TLM Concepts and Applications for Embedded Systems. Springer, November 2005.
[6]
IBM. The CoreConnect Bus Architecture. IBM, 1999.
[7]
W. Klingauf and R. Guenzel. From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling. Proc. FPT, 2005.
[8]
T. Kogel, M. Doerper, A. Wieferink, R. Leupers, G. Ascheid, and H. Meyr. A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks. Proc. CODES+ISSS, 2003.
[9]
ARM limited. AMBA AXI Protocol V1.0. ARM limited, March 2004.
[10]
C. Arnold M.Catanzariti and Ch. de Vienne. log4cxx Project. http://logging.apache.org/log4cxx/, May 2004.
[11]
ST Microelectronics. TAC: Transaction Accurate Communication. http://www.greensocs.com/TACPackage, 2005.
[12]
OCP-IP. Open Core Protocol Specification 2.0. OCP International Partnership, 2003.
[13]
M. Janssen R. Hilderink and H. Keding. Simple Version of an Abstract Bus Model. SystemC 2.0 package, January 2002.
[14]
A. Rose, S. Swan, J. Pierce, and J.M. Fernandez. Transaction Level Modeling in SystemC. OSCI TLM-WG, 2005.

Cited By

View all
  • (2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
  • (2011)A fast and effective dynamic trace-based method for analyzing architectural performanceProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950933(591-596)Online publication date: 25-Jan-2011
  • (2011)A high-throughput, high-accuracy system-level simulation framework for system on chipsVLSI Design10.1155/2011/7260142011(1-17)Online publication date: 1-Jan-2011
  • Show More Cited By

Index Terms

  1. GreenBus: a generic interconnect fabric for transaction level modelling

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '06: Proceedings of the 43rd annual Design Automation Conference
    July 2006
    1166 pages
    ISBN:1595933816
    DOI:10.1145/1146909
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 24 July 2006

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. SoC
    2. SystemC
    3. TLM
    4. on-chip communication

    Qualifiers

    • Article

    Conference

    DAC06
    Sponsor:
    DAC06: The 43rd Annual Design Automation Conference 2006
    July 24 - 28, 2006
    CA, San Francisco, USA

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 08 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
    • (2011)A fast and effective dynamic trace-based method for analyzing architectural performanceProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950933(591-596)Online publication date: 25-Jan-2011
    • (2011)A high-throughput, high-accuracy system-level simulation framework for system on chipsVLSI Design10.1155/2011/7260142011(1-17)Online publication date: 1-Jan-2011
    • (2011)Models of Computation and LanguagesEmbedded Systems Design Based on Formal Models of Computation10.1007/978-94-007-1594-3_2(7-41)Online publication date: 21-May-2011
    • (2010)TLM automation for multi-core designProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899888(717-724)Online publication date: 18-Jan-2010
    • (2009)Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal modelProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509764(558-563)Online publication date: 19-Jan-2009
    • (2009)Adaptive Interconnect Models for Transaction-Level SimulationLanguages for Embedded Systems and their Applications10.1007/978-1-4020-9714-0_10(149-165)Online publication date: 2009
    • (2008)Accuracy-adaptive simulation of transaction level modelsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403566(788-791)Online publication date: 10-Mar-2008
    • (2008)On Construction of Cycle Approximate Bus TLMsEmbedded Systems Specification and Design Languages10.1007/978-1-4020-8297-9_3(31-43)Online publication date: 2008
    • (2007)Embedded software development on top of transaction-level modelsProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289827(27-32)Online publication date: 30-Sep-2007
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media