skip to main content
10.1145/1146909.1147157acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

Standard cell library optimization for leakage reduction

Published: 24 July 2006 Publication History

Abstract

Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. We propose a library optimization approach involving generation of additional variants for each cell master, by biasing gate-lengths of devices. We employ transistor-level gate-length assignment to exploit asymmetries in standard cell circuit topology as well slack distribution of the design. The enhanced library is used by a power optimizer to reduce design leakage without violating any timing constraints. Such transistor-level optimization of cell libraries offers significantly better leakage-delay tradeoff than simple cell-level biasing (CLB) proposed previously. Experimental results on benchmarks show transistor-level biasing (TLB) can improve the CLB leakage optimization results by 8-17%. There is a corresponding improvement in design leakage distribution as well.

References

[1]
S. Narendra et. al., "Leakage Issues in IC Design: Trends, Estimation and Avoidance", Tutorial, ICCAD, 2003.
[2]
S. Mutah, T. Douseki Y. Marsuya, T. Aoki and S. Shigematru. "I-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, JSSC 1995. Vol. 30. No. 8.00. 847--854.
[3]
Y. Oowalti et al. "A sub-0.1um Circuit Design with Substrate-Over-Biasing". ISSCC. 1998, pp. 88--89.
[4]
S. Sirichotiyakul et. al., "Duet: An accurate leakage estimation and optimization tool for dual-Vt circuits", IEEE Transactions on VLSI Systems, pp. 79--90, April 2002.
[5]
P. Gupta et al, " A practical transistor-level dual threshold voltage assignment methodology", ISQED, 2005, pp 421--426.
[6]
L. Wei et al, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits'', DAC. 1998. pp. 489--494.
[7]
P. Gupta et al, "Selective gate-length biasing for cost-effective runtime leakage control", DAC, 2004. pp. 327--330.
[8]
A. Salz, M. Horowitz, "IRSIM: an incremental MOS switch-level simulator", DAC, 1989. pp. 173--178
[9]
F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. International Symposium on Circuits and Systems (ISCAS), pp. 1229--1234, IEEE, 1989.
[10]
http://www.opencores.org/project

Cited By

View all
  • (2008)Invited paperIntegration, the VLSI Journal10.1016/j.vlsi.2007.09.00141:3(319-339)Online publication date: 1-May-2008
  • (2008)Nano‐CMOS Design Tools: Beyond Model‐Based Analysis and CorrectionNano‐CMOS Design for Manufacturabililty10.1002/9780470382820.ch7(333-380)Online publication date: 7-Feb-2008

Index Terms

  1. Standard cell library optimization for leakage reduction

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '06: Proceedings of the 43rd annual Design Automation Conference
    July 2006
    1166 pages
    ISBN:1595933816
    DOI:10.1145/1146909
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 24 July 2006

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. gate-length biasing
    2. leakage reduction
    3. library optimization

    Qualifiers

    • Article

    Conference

    DAC06
    Sponsor:
    DAC06: The 43rd Annual Design Automation Conference 2006
    July 24 - 28, 2006
    CA, San Francisco, USA

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)1
    Reflects downloads up to 17 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2008)Invited paperIntegration, the VLSI Journal10.1016/j.vlsi.2007.09.00141:3(319-339)Online publication date: 1-May-2008
    • (2008)Nano‐CMOS Design Tools: Beyond Model‐Based Analysis and CorrectionNano‐CMOS Design for Manufacturabililty10.1002/9780470382820.ch7(333-380)Online publication date: 7-Feb-2008

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media