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Fast falsification based on symbolic bounded property checking

Published: 24 July 2006 Publication History

Abstract

Symbolic property verification is an increasingly popular debugging method based on Binary Decision Diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper we present an accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is a novel one as it is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation.

References

[1]
S. Ben-David, T. Heyman, O. Grumberg, and A. Schuster. Scalable distributed on-the-fly symbolic model checking. In W. A. Hunt, Jr. and S. D. Johnson, editors, Formal Methods in Computer-Aided Design, Third International Conference, volume 1954 of Lecture Notes in Computer Science, pages 390--404. Springer, 2000.]]
[2]
A. Biere, A. Cimatti, E. M. Clarke, O. Strichman, and Y. Zhu. Bounded model checking. In M. Zelkowitz, editor, Highly Dependable Software, volume 58 of Advances in Computers. Academic Press, 2003.]]
[3]
R. Bloem, K. Ravi, and F. Somenzi. Symbolic guided search for CTL model checking. In DAC '00: Proceedings of the 37th conference on Design automation, pages 29--34, New York, NY, USA, 2000. ACM Press.]]
[4]
B. Bollig and I. Wegener. Partitioned BDDs vs. other BDD models. In ACM/IEEE International Workshop on Logic Synthesis (IWLS), May 1997.]]
[5]
R. E. Bryant. Symbolic boolean manipulation with ordered binary-decision diagrams. ACM Computing Surveys, 24(3):293--318, September 1992.]]
[6]
J. Burch, E. Clarke, and D. Long. Symbolic model checking with partitioned transition relations. In A. Halaas and P. Denyer, editors, International Conference on Very Large Scale Integration (VLSI), pages 49--58, Edinburgh, Scotland, August 1991. IFIP Transactions, North-Holland.]]
[7]
J. Burch, E. Clarke, K. L. McMillan, D. Dill, and L. Hwang. Symbolic Model Checking: 1020 States and Beyond. Information and Computing, 98(2):142--170, June 1992.]]
[8]
J. R. Burch, E. M. Clarke, and D. E. Long. Representing circuits more efficiently in symbolic model checking. In 28th Conference on Design Automation, pages 403--407. ACM Press, 1991.]]
[9]
G. Cabodi, P. Camurati, L. Lavagno, and S. Quer. Disjunctive partitioning and partial iterative squaring: An effective approach for symbolic traversal of large circuits. In 34th Conference on Design Automation, pages 728--733. ACM Press, 1997.]]
[10]
E. M. Clarke, O. Grumberg, and D. E. Peled. Model Checking. The MIT Press, December 1999.]]
[11]
D. Geist and I. Beer. Efficient model checking by automated ordering of transition relation. In D. L. Dill, editor, Conference on Computer Aided Verification (CAV), volume 818 of Lecture Notes in Computer Science, pages 299--310, Stanford, California, USA, June 1994. Springer-Verlag.]]
[12]
O. Grumberg, T. Heyman, and A. Schuster. A work-efficient distributed algorithm for reachability analysis. In W. A. Hunt Jr. and F. Somenzi, editors, Computer Aided Verification, 15th International Conference, volume 2725 of Lecture Notes in Computer Science, pages 54--66. Springer Verlag, 2003.]]
[13]
A. Narayan, J. Jain, M. Fujita, and A. L. Sangiovanni-Vincentelli. Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for boolean functions. In 1996 IEEE/ACM International Conference on CAD, pages 547--554. ACM and IEEE Computer Society Press, 1996.]]
[14]
P. M. Peranandam, P. K. Nalla, R. J. Weiss, J. Ruf, T. Kropf, and W. Rosenstiel. Overlap reduction in symbolic system traversal. In IEEE International High Level Design Validation and Test Workshop 2005 (HLDVT 05), November 2005.]]
[15]
K. Ravi, K. L. McMillan, T. R. Shiple, and F. Somenzi. Approximation and decomposition of binary decision diagrams. In 35th Conference on Design Automation, pages 445--450. ACM Press, 1998.]]
[16]
K. Ravi and F. Somenzi. High-density reachability analysis. In 1995 IEEE/ACM International Conference on CAD, pages 154--158. ACM and IEEE Computer Society Press, 1995.]]
[17]
K. Ravi and F. Somenzi. Hints to accelerate symbolic traversal. In CHARME '99: Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pages 250--264, London, UK, 1999. Springer-Verlag.]]
[18]
J. Ruf, D. W. Hoffmann, T. Kropf, and W. Rosenstiel. Simulation-guided property checking based on a multi-valued AR-automata. In W. Nebel and A. Jerraya, editors, Design, Automation and Test in Europe 2001, pages 742--748. IEEE Press, 2001.]]
[19]
J. Ruf, P. M. Peranandam, T. Kropf, and W. Rosenstiel. Bounded property checking with symbolic simulation. In Forum on Specification and Design Languages 2003, 2003.]]
[20]
D. Sahoo, S. K. Iyer, J. Jain, C. Stangier, A. Narayan, D. L. Dill, and E. A. Emerson. A partitioning methodology for BDD-based verification. In A. J. Hu and A. K. Martin, editors, Formal Methods in Computer-Aided Design, Fifth International Conference, volume 3312 of Lecture Notes in Computer Science, pages 399--413. Springer, 2004.]]
[21]
F. Somenzi. CUDD: CU decision diagram package, release 2.4.0. http://vlsi.colorado.edu/~fabio/CUDD, 2004.]]
[22]
C. H. Yang and D. L. Dill. Validation with guided search of the state space. In Design Automation Conference (DAC), pages 599--604, San Francisco, CA, June 1998. ACM/IEEE.]]

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    cover image ACM Conferences
    DAC '06: Proceedings of the 43rd annual Design Automation Conference
    July 2006
    1166 pages
    ISBN:1595933816
    DOI:10.1145/1146909
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    Published: 24 July 2006

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    1. fast falsification
    2. guiding
    3. property checking

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    July 24 - 28, 2006
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