Raghavendra Rao Loka
Abstract
Compiling hardware models to machine code poses some unusual problems. While compilers for traditional programming languages are well understood, they tend to take very long to compile the C code generated from hardware models. The code generated from hardware models, unlike in the inputs seen by traditional compilers, have too many simple routines. These routines have much simpler control flow, and the patterns of the routines are repeated several times over. This paper discusses the approaches developed at Synopsys to compile these routines as optimally as traditional compilers, but taking less time.
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Index Terms
- Compilation reuse and hybrid compilation: an experiment
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