Article

Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

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M. Hübner,

J. BeckerAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 1 - 4

https://doi.org/10.1145/1150343.1150350

Published: 28 August 2006 Publication History

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Abstract

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. This feature enables the substitution of the reconfigurable architecture within a configuration area on the chip. Beneficial here is that the architecture can be adapted to the actual demand of an application while run-time. High performance, flexibility and adaptivity of these devices raise the interest in academic research and also in industrial fields of application. This new method for designing systems isn't supported very well by tools until now. This tutorial should help designers as well as researchers in developing dynamic and partial reconfigurable systems and increase the number of area of applications exploiting this very promising methodology. As an example the design of an on-demand reconfigurable system for inner cabin automotive application will be presented.

References

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J. Becker, M. Hübner, M. Ullmann: "Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations", VLSI03, Darmstadt, Sep. 03

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M. Ullmann, M. Huebner, B. Grimm, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fee

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J. Becker, M. Hübner, M. Ullmann: "Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations", SBCCI03, Sao Paulo, Sep. 03

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M. Hübner, K. Paulsson, M. Stitz, J. Becker: "Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs", ARCS05, Innsbruck, Austria

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Cited By

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Nanda IMidhunchakkaravarthy J(2023)Execution of Reconfiguration System on Chip Design for Internet of Things2023 5th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)10.1109/ICAC3N60023.2023.10541602(1642-1646)Online publication date: 15-Dec-2023
https://doi.org/10.1109/ICAC3N60023.2023.10541602
Nanda IAdhikari N(2017)Application and performance of FPGA using partial reconfiguration with Xilinx PlanAhead2017 IEEE Transportation Electrification Conference (ITEC-India)10.1109/ITEC-India.2017.8333891(1-4)Online publication date: Dec-2017
https://doi.org/10.1109/ITEC-India.2017.8333891
Nanda IPujari SPanda C(2015)Implementation of Math PRR and LED Processing Using Xilinx PlanAhead2015 International Conference on Computing Communication Control and Automation10.1109/ICCUBEA.2015.189(955-958)Online publication date: Feb-2015
https://doi.org/10.1109/ICCUBEA.2015.189
Show More Cited By

Index Terms

Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Dynamic reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We ...

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Published In

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 28 August 2006

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SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Nanda IMidhunchakkaravarthy J(2023)Execution of Reconfiguration System on Chip Design for Internet of Things2023 5th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)10.1109/ICAC3N60023.2023.10541602(1642-1646)Online publication date: 15-Dec-2023
https://doi.org/10.1109/ICAC3N60023.2023.10541602
Nanda IAdhikari N(2017)Application and performance of FPGA using partial reconfiguration with Xilinx PlanAhead2017 IEEE Transportation Electrification Conference (ITEC-India)10.1109/ITEC-India.2017.8333891(1-4)Online publication date: Dec-2017
https://doi.org/10.1109/ITEC-India.2017.8333891
Nanda IPujari SPanda C(2015)Implementation of Math PRR and LED Processing Using Xilinx PlanAhead2015 International Conference on Computing Communication Control and Automation10.1109/ICCUBEA.2015.189(955-958)Online publication date: Feb-2015
https://doi.org/10.1109/ICCUBEA.2015.189
Marques NRabah HJovanovic SDabellani EWeber S(2013)Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013)10.1109/AHS.2013.6604240(156-163)Online publication date: Jun-2013
https://doi.org/10.1109/AHS.2013.6604240
Cancare FBartolini DCarminati MSciuto DSantambrogio M(2012)On the Evolution of Hardware Circuits via Reconfigurable ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/2392616.23926205:4(1-22)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1145/2392616.2392620
Miele Adi Torino P(2010)A software framework for dynamic self-repair in embedded SoCs exploiting reconfigurable devicesProceedings of the 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) - Volume 0210.1109/AQTR.2010.5520834(1-6)Online publication date: 28-May-2010
https://dl.acm.org/doi/10.1109/AQTR.2010.5520834
Whitham JAudsley NSchoeberl MHiguera-Toledano MSchoeberl M(2009)Using hardware methods to improve time-predictable performance in real-time Java systemsProceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems10.1145/1620405.1620424(130-139)Online publication date: 23-Sep-2009
https://dl.acm.org/doi/10.1145/1620405.1620424
El-Araby EGonzalez IEl-Ghazawi T(2009)Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/1462586.14625901:4(1-23)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1145/1462586.1462590
Patel HKim YTodd McDonald JStarman L(2009)Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis2009 International Conference on Field Programmable Logic and Applications10.1109/FPL.2009.5272253(391-396)Online publication date: Aug-2009
https://doi.org/10.1109/FPL.2009.5272253
Rosti A(2009)Dissemination of MORPHEUS ResultsDynamic System Reconfiguration in Heterogeneous Platforms10.1007/978-90-481-2427-5_20(251-259)Online publication date: 2009
https://doi.org/10.1007/978-90-481-2427-5_20
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Recommendations

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

Partial dynamic reconfiguration framework for FPGAs through remote access

Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation

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