Cited By
View all- Yuan ZMa YBian J(2012)SMPPProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum10.1109/IPDPSW.2012.57(443-448)Online publication date: 21-May-2012
A fast SAT solver algorithm best suited to reconfigurable hardware
Pages 131 - 136
Abstract
The majority of the existing reconfigurable hardware SAT solvers employ some variation of the Davis-Putnam algorithm; we propose a new algorithm for organizing the search in SAT Solvers best suited to reconfigurable architectures due to its vector-like operations. Its essence is to view each negated clause as a cube in the n-dimensional Boolean search space, and realizing that each of these clause-cubes denotes a sub-region of the search space where no satisfying assignments can be found. Starting from the universal cube, which represents the whole space, we systematically subtract all clause-cubes until we end up with a satisfying cube or an empty cube if the SAT formula is unsatisfiable. The algorithm for cube subtraction is the D-Sharp algorithm. We implemented this strategy in the well-known zChaff SAT solver. Improvements in execution time and number of aborted instances have been observed for the new algorithm. The test suite includes several instances from IBM-CNF BMC and Microprocessor's Formal Verification benchmarks. Given the breadth of the experimental software evaluation, we claim that D-Sharp subtraction search is an effective algorithm for improving the performance of SAT solvers and due to its data structure and bit-to-bit operations it is very well suited to reconfigurable hardware implementations. Design Automation (EDA).
References
[1]
Miroslav N. Velev and Randal E. Bryant. Efective use of Boolean Satisfiability. In Proc.of DAC pp.226--231, 2001.
[2]
A. Biere, A. Cimatti, E. Clarke and Y. Zhu: Symbolic Model Checking without BDDs. In Proc. of TACAS pp. 193--207, 1999
[3]
SAT contest. http://www.satcompetition.org/
[4]
M. Davis, G. Logemann, and D. Loveland: A machine program for theorem proving. In Communications of the ACM, (5):394--397, 1962.
[5]
Iouliia Skliarova. and Antonio Brito Ferrari: Reconfigurable Hardware SAT Solvers: A Survey of Systems. In: IEEE Trans. on Computers, vol. 53, no. 11, Nov. 2004.
[6]
W.H. Yung, Y.W. Seung, K.H. Lee, and P.H.W. Leong, A Runtime Reconfigurable Implementation of the GSAT Algorithm, In Proc. 9th WFPLA, pp. 526--531, 1999.
[7]
P.H.W. Leong, C.W. Sham, W.C. Wong, H.Y. Wong, W.S. Yuen, and M.P. Leong, A Bitstream Reconfigurable FPGA Implementation of the WSAT Algorithm, in IEEE Trans. VLSI Systems, vol. 9, no. 1, pp. 197--201, 2001.
[8]
R.H.C. Yap, S.Z.Q. Wang, and M.J. Henz. Hardware Implementations of Real-Time Reconfigurable WSAT Variants, In Proc. 13th FPLA, pp. 488--496, 2003.
[9]
Y. Hamadi and D. Merceron. Reconfigurable Architectures: A New Vision for Optimization Problems, In Proc. 3rd PPCP, pp. 209--215, 1997.
[10]
M. Abramovici and D. Saab. Satisfiability onReconfigurable Hardware, In Proc. 7th FPLA, pp. 448--456, 1997.
[11]
A. Rashid, J. Leonard, and W.H. Mangione-Smith. Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability. In Proc. Sixth IEEE Symp. FPGAs for Custom Computing Machines, pp. 196--205, 1998.
[12]
T. Suyama, M. Yokoo, H. Sawada, and A. Nagoya. Solving Satisfiability Problems Using Reconfigurable Computing. In IEEE Trans. VLSI Systems, vol. 9, pp. 109--116, 2001.
[13]
J. de Sousa, J.P. Marques-Silva, and M. Abramovici. A Configware/ Software Approach to SAT Solving In Proc. Ninth IEEE Int'l Symp. Field-Programmable Custom Computing Machines, 2001.
[14]
P. Zhong. Using Configurable Computing to Accelerate Boolean Satisfiability. In PhD dissertation, Dept. of Electrical Eng., Princeton Univ., 1999.
[15]
A. Dandalis and V.K. Prasanna. Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. In ACM Trans. Design Automation of Electronic Systems, vol. 7, no. 4, pp. 547--562, Oct. 2002.
[16]
O. Mencer and M. Platzner. Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment. In Proc. 32nd-HICSS-32, 1999.
[17]
Ioullia Skliarova and Antonio B. Ferrari. A Software /Reconfigurable Hardware SAT Solver. In IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4, pp. 408--419, Apr. 2004.
[18]
M. Boyd and T. Larrabee. ELVIS - a Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. In Proc. Eight IEEE Int'l Symp. Field-Programmable Custom Computing Machines, 2000.
[19]
L.M.Silva and K.A. Sakallah. GRASP: A Search Algorithm for Propositional Satisfiability. In IEEE Trans. Computers, vol. 48, no. 5, pp. 506--521, May 1999.
[20]
Beame, P., Kautz, H., Sabharwal, A. Towards Understanding and Harnessing the Potential of Clause Learning. In JAR, Vol. 22, pp. 319--351, Dec. 2004
[21]
Nachum Dershowitz, Ziyad Hanna, and Alexander Nadel, A Clause-Based Heuristic for SAT Solvers. In Proc. SAT05 pp. 43--60, June 2005
[22]
M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik: Chaff: Engineering an Efficient SAT Solver. In Proc. of 38th DAC pp. 530--535, 2001.
[23]
Y.Novikov E.Goldberg: Berkmin: a Fast and Robust Sat-Solver. In Proc. of DATE2002 p. 142, 2002.
[24]
Iouliia Skliarova. Arquiteturas Reconfiguráveis para Problemas de Optimização Combinatória. In: PHD Thesis, Universidade de Aveiro, 2003. (Portuguese Version)
[25]
S.J. Hong and D.L. Ostapko: Fault Analysis and Test Generation for PLAs. In IEEE Trans. on Computers, vol C-28, n. 9, Sep. 1979
[26]
J. E. Smith: Detection of Faults in Programmable Logic Arrays. In IEEE Trans. on Computers, vol C-28, n.11, Nov. 1979
[27]
zChaff: http://www.princeton.edu/~chaff/zChaff.html
[28]
http://www.haifa.il.ibm.com/projects/verification/RB_Home page/bmcbenchmarks.html
[29]
http://www.ece.cmu.edu/~mvelev/sat-benchmarks.html
[30]
http//www.intellektik.informatik.tudarmstadt.de/SATLIB/ben chm.html
Index Terms
- A fast SAT solver algorithm best suited to reconfigurable hardware
Recommendations
A modular CNF-based SAT solver
SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system designThe state-of-the-art SAT solvers, such as Chaff [11], zChaff [18], BerkMin [5], and Minisat [2] usually share the same core techniques, for instance: the watched literals structures conflict clause recording and non-chronological backtracking. ...
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
DAC '09: Proceedings of the 46th Annual Design Automation ConferenceBoolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solvers are based on the Davis-Putnam-Logemann-Loveland (DPLL) algorithm and ...
Making deduction more effective in SAT solvers
Satisfiability (SAT) solvers often benefit from transformations of the formula to be decided that allow them to do more through deduction and decrease their reliance on enumeration. For formulae in conjunctive normal form, subsumed clauses may be ...
Comments
Information & Contributors
Information
Published In
August 2006
248 pages
ISBN:1595934790
DOI:10.1145/1150343
- General Chair:
- Claudionor Coelho,
- Program Chairs:
- Ricardo Jacobi,
- Juergen Becker
Copyright © 2006 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 28 August 2006
Check for updates
Author Tags
Qualifiers
- Article
Conference
SBCCI06: 19th Symposium on Integrated Circuits and System Design
August 28 - September 1, 2006
MG, Ouro Preto, Brazil
Acceptance Rates
Overall Acceptance Rate 133 of 347 submissions, 38%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 311Total Downloads
- Downloads (Last 12 months)2
- Downloads (Last 6 weeks)0
Reflects downloads up to 07 Mar 2025
Other Metrics
Citations
Cited By
View all- Yuan ZMa YBian J(2012)SMPPProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum10.1109/IPDPSW.2012.57(443-448)Online publication date: 21-May-2012
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in