Article

Fast disjoint transistor networks from BDDs

Authors:

Leomar S. da Rosa Junior,

Felipe S. Marques,

Tiago M. G. Cardoso,

Renato P. Ribas,

Sachin S. Sapatnekar,

André I. ReisAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 137 - 142

https://doi.org/10.1145/1150343.1150381

Published: 28 August 2006 Publication History

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Abstract

In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks. The reduced length of transistor stacks leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs. Delay and area results are presented showing the impact of the proposed strategy.

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Cited By

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Kagaris D(2016)MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD ToolIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244867535:1(114-127)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2448675
Sharmila RJothikumar R(2016)Notice of Violation of IEEE Publication Principles - A novel algorithm to implement transistor networks with reduced number of switches2016 10th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2016.7726946(1-6)Online publication date: Jan-2016
https://doi.org/10.1109/ISCO.2016.7726946
Callegaro VMarques FKlock Cda Rosa LRibas RReis AMartino JAraújo GOrailoglu AKlein F(2010)SwitchCraftProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854167(49-53)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1145/1854153.1854167
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Index Terms

Fast disjoint transistor networks from BDDs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Digital switches
      1. Logic families

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Published In

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 August 2006

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SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Kagaris D(2016)MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD ToolIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244867535:1(114-127)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TCAD.2015.2448675
Sharmila RJothikumar R(2016)Notice of Violation of IEEE Publication Principles - A novel algorithm to implement transistor networks with reduced number of switches2016 10th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2016.7726946(1-6)Online publication date: Jan-2016
https://doi.org/10.1109/ISCO.2016.7726946
Callegaro VMarques FKlock Cda Rosa LRibas RReis AMartino JAraújo GOrailoglu AKlein F(2010)SwitchCraftProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854167(49-53)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.1145/1854153.1854167
Cardoso TMarques FRibas RReis Ada Rosa L(2008)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479696(47-52)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479696
da Rosa LReis ARibas RMarques FSchneider FPetraglia APedroni VCauwenberghs G(2007)A comparative study of CMOS gates with minimum transistor stacksProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284511(93-98)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284511
Kagaris DHaniotakis T(2007)A methodology for transistor-efficient supergate designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89524815:4(488-492)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.895248

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Index Terms

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A comparative study of CMOS gates with minimum transistor stacks

Modeling and estimating leakage current in series-parallel CMOS networks

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

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