Cache performance impacts for stack machines in embedded systems
Pages 155 - 160
Abstract
Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. However, because of its extra layer of interpretation, it is also believed that it is a slow language while being executed. Nevertheless, when this execution is done directly in hardware, Java advantages caused by its stack nature start to appear. One of these advantages concerns memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy consumption, comparing a Java processor with a RISC one based on aMIPS architecture with similar characteristics.
References
[1]
The Embedded Software Strategic Market Intelligence. Java in Embedded Systems. http://www.vdc-corp.com/
[2]
S. McAteer. Java will be the dominant handset platform. www.microjava.com/articles/perspective/zelos/.
[3]
D. Mulchandani. Java for Embedded Systems. Internet Computing, 31(10):30--39, May 1998.
[4]
Lawton, "Moving Java into Mobile Phones", Computer, vol. 35, n. 6, 2002, pp. 17--20.
[5]
P. Koopman, Stack Computers: The New Wave, Halsted Press, 1st edition, 1989
[6]
S. Segars, "Low power design techniques for microprocessors," Int. Solid-State Circuits Conf. Tutorial, 2001.
[7]
J. M. O'Connor, M. Tremblat, "Picojava-I: the Java Virtual Machine in Hardware", IEEE Micro, vol. 17, n. 2, Mar-Apr. 1997, pp. 45--53
[8]
Sun Microsystems, PicoJava-II Microarchitecture Guide, Mar. 1999.
[9]
W. Shiue, C. Chakrabarti, "Memory Design and Exploration for Low Power, Embedded Systems", The Journal of VLSI Signal Processing - Systems for Signal, Image, and Video Technology, Vol. 29, No. 3, Nov. 2001, pp. 167--178
[10]
C. Zhang, F. Vahid, W. Najjar, "A highly configurable cache architecture for embedded systems", Proceedings of the 30th annual international symposium on Computer architecture (ISCA), 2003
[11]
C. Zhang, J. Yang, F. Vahid," Low Static-Power Frequent-Value Data Caches", Proceedings of the. Design, Automation and Test in Europe Conference (DATE), 2004
[12]
R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, P. Marwedel, "Scratchpad Memory: A Design Alternative for Cache On-chip memory in Embedded Systems", Proc. of the 10th International Workshop on Hardware/Software Codesign, CODES, 2002
[13]
J. L. Hennessy, D. A. Patterson, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publishers, 3th edition, 2005
[14]
A.C.S.Beck, L. Carro, "Low Power Java Processor for Embedded Applications". In: IFIP 12th International Conference on Very Large Scale Integration, Germany, 2003
[15]
G. Reinman and N. Jouppi. Extensions to cacti, 1999. Unpublished document.
[16]
D. Gregg, J. Power, "Platform Independent Dynamic Java Virtual Machine Analysis: the Java Grande Forum Benchmark Suite", Joint ACM Java Grande - ISCOPE Conf. Proc., 2001
[17]
K. Puttaswamy, K. Choi, J. C. Park, V. J. Mooney, A. Chatterjee, P. Ellervee. "System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory", ISSS'02., October, 2002
[18]
Java Tecnology Homepage, http://java.sun.com/
[19]
GCC Homepage, http://gcc.gnu.org/
Index Terms
- Cache performance impacts for stack machines in embedded systems
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Published In
August 2006
248 pages
ISBN:1595934790
DOI:10.1145/1150343
- General Chair:
- Claudionor Coelho,
- Program Chairs:
- Ricardo Jacobi,
- Juergen Becker
Copyright © 2006 ACM.
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Publication History
Published: 28 August 2006
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SBCCI06: 19th Symposium on Integrated Circuits and System Design
August 28 - September 1, 2006
MG, Ouro Preto, Brazil
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