A cell library for low power high performance CMOS voltage-mode quaternary logic
Pages 167 - 172
Abstract
A new method to implement high performance and low power quaternary circuits using multi-threshold transistors and 3 power supply lines is presented in this work. Some specific basic gates like inverter, NMIN and NMAX circuits are presented together with a look-up table that can be used to perform any logic function. These basic circuits are used to implement arithmetic circuits. A quaternary full adder is demonstrated and compared to equivalent binary circuit showing higher speed, low consumption with a low area overhead. The circuits were simulated with the Spice tool using TSMC 0.18μm technology.
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Index Terms
- A cell library for low power high performance CMOS voltage-mode quaternary logic
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Published In
August 2006
248 pages
ISBN:1595934790
DOI:10.1145/1150343
- General Chair:
- Claudionor Coelho,
- Program Chairs:
- Ricardo Jacobi,
- Juergen Becker
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Published: 28 August 2006
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SBCCI06: 19th Symposium on Integrated Circuits and System Design
August 28 - September 1, 2006
MG, Ouro Preto, Brazil
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