Article

ByZFAD: a low switching activity architecture for shift-and-add multipliers

Authors:

Mohammad D. Mottaghi,

Ali Afzali Kusha,

Zainanabedin NavabiAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 179 - 183

https://doi.org/10.1145/1150343.1150390

Published: 28 August 2006 Publication History

Get Access

Abstract

In this paper, a low-power architecture (ByZFAD Stands for Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications include the removal of the shift of B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of the binary counter, and removal of the partial product shift. To show the efficiency of the architecture, we have compared the switching activity of the proposed architecture with that of the conventional architecture for a radix-2 shift-and-add multiplier. The results for a 32-bit multiplier show that, the proposed architecture lowers the total switching activity up to 76% when compared to the traditional architecture.

References

[1]

A. Chandrakasan, "Low-power CMOS digital design", IEEE J. Solid-State Circ., vol. 27, no. 4, April 1992, pp. 473--484.

Crossref

Google Scholar

[2]

A. Chandrakasan, "Design of portable systems," Proc. IEEE 1994 CICC, pp. 12.1.1--12.1.8.

Google Scholar

[3]

Nan-Ying Shen, Chen.O.T., "Low-power multipliers by minimizing switching activities of partial products", ISCAS 2002. IEEE International Symposium on Circuits and Systems, vol.4, pp. 93--96, May 2002.

Google Scholar

[4]

O.T. Chen, S. Wang, and Yi-Wen Wu, "Minimization of switching activities of partial products for designing low-power multipliers", IEEE Transactions on VLSI Systems, vol. 11, pp. 418--433, June 2003.

Digital Library

Google Scholar

[5]

C. Nagendra, "Power Delay characteristics of CMOS Adders," IEEE trans, VLSI systems, vol. 2, no. 3, Sept. 1994, pp. 377--381.

Digital Library

Google Scholar

[6]

B. Parhami, Computer Arithmetic Algorithms and Hardware Designs. Oxford university press, 1st edition, 2000.

Digital Library

Google Scholar

[7]

L. Junming, "A novel 10-transistor lowpower high-speed full adder cell", Proc. International Conference on Solid-State and Integrated Circuit Technology, 2001, pp. 1155--1158.

Google Scholar

[8]

M. D. Mottaghi, "Low-power ring counter based of hot-block architecture," to be published

Google Scholar

[9]

S.-W. Heo, M.-G. Kim, and Y.-S. Lee, "Study of optimized adder selection," Proc. 5th International Conference on ASIC, vol. 2, pp. 586--590, Oct. 2003.

Google Scholar

[10]

A. Sayed and H. Al-Asaad, "Survey and evaluation of low-power full-adder cells," Proc. 5th International Conference on ASIC, vol. 2, pp. 201--206, Oct. 2002.

Google Scholar

[11]

A. Shams and M. Bayoumi, "A novel high-performance CMOS 1-Bit full-adder cell", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 478--481, May 2000.

Crossref

Google Scholar

[12]

H. A. Mahmoud and M. Bayoumi, "A 10-transistor low-power high-speed full adder cell," Proc. International Symposium on Circuits and Systems, 1999, pp. 43--46.

Google Scholar

Cited By

View all

Dastjerdi-Mottaghi MNaghilou ADaneshtalab MAfzali-Kusha ANavabi Z(2006)Hot Block Ring Counter: A Low Power Synchronous Ring Counter2006 International Conference on Microelectronics10.1109/ICM.2006.373266(58-62)Online publication date: Dec-2006
https://doi.org/10.1109/ICM.2006.373266

Index Terms

ByZFAD: a low switching activity architecture for shift-and-add multipliers
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits

Recommendations

BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture

In this paper, a low-power structure called bypass zero, feed A directly (BZ-FAD) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications to the multiplier ...
A Low Power Correlator for CDMA Wireless Systems

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range 7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, ...
Enhanced-functionality multipliers

High-speed arithmetic units in modern processors are expected to support multiplication operations with integers, fractions, and floating-point numbers. This paper presents hardware designs that can perform three modes of multiplication: (1) A double-...

Comments

Information & Contributors

Information

Published In

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 August 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

SBCCI06

Sponsor:

SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

Acceptance Rates

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
305
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Dastjerdi-Mottaghi MNaghilou ADaneshtalab MAfzali-Kusha ANavabi Z(2006)Hot Block Ring Counter: A Low Power Synchronous Ring Counter2006 International Conference on Microelectronics10.1109/ICM.2006.373266(58-62)Online publication date: Dec-2006
https://doi.org/10.1109/ICM.2006.373266

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture

A Low Power Correlator for CDMA Wireless Systems

Enhanced-functionality multipliers

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations