Single event transients in dynamic logic

Radiation effects, like Single Event Transients (SET), are increasingly affecting integrated circuits as device dimensions are scaling down. With decreasing dimensions and supply voltages, the charge used to store information decreases, turning the circuits more sensitive to the transient currents generated by energetic particle hits. This is particularly important for dynamic logic, which relies on proper charge storage at circuit nodes.In this work the sensitivity of dynamic logic to Single Event Transients is studied and modeled. The single event upset (SEU) mechanism in both dynamic and static MOS circuits is studied starting from circuit simulation. From this study it is shown that standard dynamic logic circuits are much more sensitive to SET than static circuits. However, the implementation of a keeper technique may greatly reduce the sensitive of dynamic logic, increasing its robustness against SET.Furthermore, an accurate and computationally efficient analytical model for the evaluation of static and dynamic circuit sensitivity to SEU is presented. The model may be used in early design stages, helping to design circuits with increased tolerance to SET. The proposed model predicts whether or not a particle hit generates a SET which may be interpreted as a logical signal in the circuit. Good agreement between model and electrical simulation results is found.