Arthur Pereira Frantz
Luigi Carro
ABSTRACT
As the complexity of designs increases and the technology scales down into the deep sub-micron domain, devices and interconnections are subject to new types of malfunctions and failures. This work intends to evaluate the effect of Single Event Upsets (SEUs) and crosstalk faults in a Network-on-Chip switch by performing fault injection simulations, allowing an accurate analysis of the impact of these faults over the switch service. The results show that such faults might affect the switch behavior, with errors ranging from simple loss of packets up to the permanent interruption of the switch service.
- Benini L.; Micheli. G. D.; "Networks on Chips: A New SoC Paradigm". IEEE Computer, Vol. 35, January, 2002, pp. 70--78. Google Scholar
Digital Library
- Dally, W. J.; Towles, B.; "Route Packets, Not Wires: On-Chip Interconnection Networks". In: Design Automation Conference, 2001, Proceedings' pp. 684--689, 2001. Google ScholarDigital Library
- Duato, J.; Yalamanchili, S.; Ni, L.; Interconnection Networks: An Engineering Approach". IEEE Computer Society, Los Alamitos, CA 1997. Google ScholarDigital Library
- Murali, S.; Theocharides, T.; Vijaykrishnan, N.; Irwin, M. J.; Benini, L.; De Micheli, G.; "Analysis of error recovery schemes for networks on chips", IEEE Design&Test of Computers, Volume 22, Issue 5, Sept.-Oct. 2005, pp. 434--442. Google ScholarDigital Library
- Acquaviva, A.; Bogliolo, A.; "A Bottom-Up Approach to On-Chip Signal Integrity", Lecture Notes in Computer Science, Volume 2799, pp. 540--549, Jan 2003.Google ScholarCross Ref
- Nicolaidis, M.; "Design for soft error mitigation", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 3, Sept. 2005, pp. 405--418.Google ScholarCross Ref
- Kastensmidt, F., Carro, L., Reis, R.; Fault-Tolerance Techniques for SRAM-based FPGAs, Series: Frontiers in Electronic Testing, Springer, Vol. 32, 2006. 180 p. Google ScholarDigital Library
- Rossi, D.; Metra, C.; Nieuwland, A. K.; Katoch, A.; "Exploiting ECC redundancy to minimize crosstalk impact", IEEE Design&Test of Computers, Volume 22, Issue 1, Jan 2005, pp. 59--70. Google ScholarDigital Library
- Nieuwland, A. K.; Katoch, A.; Rossi, D.; Metra, C.; "Coding techniques for low switching noise in fault tolerant busses", In: 11th IEEE International On-Line Testing Symposium, 2005. Proceedings.. pp. 183--189, 6-8 July 2005. Google ScholarDigital Library
- Bertozzi, D.; Benini, L.; De Micheli, G.; "Low power error resilient encoding for on-chip data buses", In: Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings.. pp. 102--109 , 4-8 March 2002. Google ScholarDigital Library
- Lajolo, M.; "Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 9, Issue 6, Dec. 2001, pp. 974--982. Google ScholarDigital Library
- Tamhankar, R. R.; Murali, S.; De Micheli, G.; "Performance driven reliable link design for networks on chips", In: Asia and South Pacific Design Automation Conference, 2005. Proceedings.. pp. 749--754, Volume 2, 18-21 Jan. 2005. Google ScholarDigital Library
- Marculescu, R.; "Networks-on-chip: the quest for on-chip fault-tolerant communication", 2003. In: IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.. pp. 8-12, 20--21 Feb. 2003. Google ScholarDigital Library
- Dumitras, T.; Kerner, S.; Marculescu, R.; "Towards on-chip fault-tolerant communication", In: Asia and South Pacific Design Automation Conference, 2003. Proceedings.. pp. 225--232, 21-24 Jan. 2003. Google ScholarDigital Library
- Bertozzi, D.; Benini, L.; De Micheli, G.; "Error control schemes for on-chip communication links: the energy-reliability tradeoff", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 6, June 2005, pp. 818--831. Google ScholarDigital Library
- Perez, J.; Reorda, M. S.; Violante, M.; "Early, Accurate Dependability Analysis of CAN-Based Networked Systems", IEEE Design&Test of Computers, Volume 23, Issue 1, Jan. 2006. Google ScholarDigital Library
- Nicolaidis, M.; "Design for soft error mitigation", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 3, Sept. 2005.Google ScholarCross Ref
- Cuviello, M.; Dey, S.; Bai, X.; Zhao, Y.; "Fault modeling and simulation for crosstalk in system-on-chip interconnects", In: 1999 IEEE/ACM International conference on Computer-Aided Design. Digest of Technical Papers, pp. 297--303, 7-11 Nov. 1999. Google ScholarDigital Library
- Zeferino, C. A., Susin, A. A., "SoCIN: A Parametric and Scalable Network-on-Chip". In: 17th Symposium on Integrated Circuits and Systems (SBCCI), 2003. Proceedings.. pp. 169--174, 2003. Google ScholarDigital Library
Index Terms
- Evaluation of SEU and crosstalk effects in network-on-chip switches
Recommendations
Crosstalk- and SEU-Aware Networks on Chips
This article proposes the use of mixed hardware-software solutions to simultaneously address crosstalk faults and single-event upsets in on-chip networks. After analyzing the susceptibility of routers to these faults, the authors propose a software-...
SET and SEU performance of single, double, triple and quadruple-gate junctionlessFETs using numerical simulations
In this paper, the relation between the number of gates and radiation resiliency, in Junctionless (JLT) devices, is investigated using 3D-TCAD simulation. JLT Devices having single, double, triple and quadruple-gate JLTs are studied for their single-...
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects
DFT '06: Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI SystemsThe paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnects ...
Comments