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A low-cost memory remapping scheme for address bus protection

Published: 16 September 2006 Publication History

Abstract

The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryption keys or proprietary algorithms. Addresses can be observed by attaching a hardware device on the bus that passively monitors the bus transaction. Such side-channel attacks should be given rising attention especially in a distributed computing environment, where remote servers running sensitive programs are not within the physical control of the client.Two previously proposed hardware techniques tackled this problem through randomizing address patterns on the bus. One proposal permutes a set of contiguous memory blocks under certain conditions, while the other approach randomly swaps two blocks when necessary. In this paper, we present an anatomy of these attempts and show that they impose great pressure on both the memory and the disk. This leaves them less scalable in high-performance systems where the bandwidth of the bus and memory are critical resources. We propose a lightweight solution to alleviating the pressure without compromising the security strength. The results show that our technique can reduce the memory traffic by a factor of 10 compared with the prior scheme, while keeping almost the same page fault rate as a baseline system with no security protection.

References

[1]
DS5002FP secure microprocessor chip data sheet.]]
[2]
http://www.buyya.com/ecogrid.]]
[3]
http://www.micron.com.]]
[4]
http://www.modchip.com.]]
[5]
2.5-inch enterprise disc drives. Technology Paper, Feb 2005.]]
[6]
IA-32 Intel Architecture Software Developer's Manual, Vol. 3A, Part 1. ftp://download.intel.com/design/Pentium4/manuals/25366818.pdf, Jan 2006.]]
[7]
T. M. Austin. The SimpleScalar Toolset. http://www.simplescalar.com, Simplescalar LLC.]]
[8]
B. Barak, O. Goldreich, R. Impagliazzo, and etc. On the (im)possibility of obfuscating programs. In CRYPTO, pages 1--18.J, 2001.]]
[9]
C. Collberg, C. Thomborson, and D. Low. A taxonomy of obfuscating transformations. Technical Report 148, University of Auckland, 1997.]]
[10]
V. Cuppu, B. Jacob, B. Davis, and T. Mudge. High-Performance DRAMs in Workstation Environments. IEEE Trans. on Computer, 50(11):1133--1153, 2001.]]
[11]
V. Cuppu, B. L. Jacob, B. Davis, and T. N. Mudge. A Performance Comparison of Contemporary DRAM Architectures. In the 26th International symposium of Computer Architecture, pages 222--233, 1999.]]
[12]
B. Gassend, G. E. Suh, D. Clarke, M. van Dijk, and S. Devadas. Caches and hash trees for efficient memory integrity verification. In The 9th International Symposium on High Performance Computer Architecture, pages 295--306, 2003.]]
[13]
O. Goldreich. Towards a theory of software protection and simulation by oblivious rams. In The 19th Annual ACM Symposium on Theory of Computing, pages 182--194, 1987.]]
[14]
O. Goldreich and R. Ostrovsky. Software protection and simulation on oblivious rams. Journal of the ACM, 43(3):431--473, May 1996.]]
[15]
P. Kocher. Timing attacks on implementations of diffie-hellman, rsa, dss, and other systems. In International Cryptology Conference, 1996.]]
[16]
M. G. Kuhn. The trustno1 cryptoprocessor concept. Technical Report CS555 Report, Purdue University, 1997.]]
[17]
M. G. Kuhn. Cipher instruction search attack on the bus-encryption security microcontroller ds5002fp. IEEE Transactions on Computers, 47(10):1153--1157, Oct 1998.]]
[18]
D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell, and M. Horowitz. Architectural Support for Copy and Tamper Resistant Software. In the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 168--177, 2000.]]
[19]
C. McClure. Software reuse planning by way of domain analysis. Technical Paper, Extended Intelligence, Inc. http://www.reusability.com.]]
[20]
A. Nanda, K. S. Kwok-Ken Mak, R. K. Sahoo, V. Soundararajan, and T. B. Smith. MemorIES: A programmable, Real-time Hardware Emulation Tool for Multiprocessor Server Design. In The Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 37--48, November 2000.]]
[21]
D. A. Osvik, A. Shamir, and E. Tromer. Cache attacks and countermeasures: the case of aes. In RSA Conference, February 2006.]]
[22]
C. Percival. Cache missing for fun and profit. In BSDCan 2005, 2005.]]
[23]
X. Qiu and M. Dubois. Towards Virtually-Addressed Memory Hierarchies. In the 7th International Symposium on High-Performance Computer Architecture, pages 51--62, 2001.]]
[24]
X. Qiu and M. Dubois. Tolerating late memory traps in dynamically scheduled processors. IEEE Transactions on Computers, 53(6):732--743, June 2004.]]
[25]
X. Qiu and M. Dubois. Moving address translation closer to memory in distributed shard-memory multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 16(7):612--623, July 2005.]]
[26]
W. Shi, H.-H. S. Lee, M. Ghosh, C. Lu, and A. Boldyreva. High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. In Proceedings of the 32nd International Symposium on Computer Architecture, pages 14--24, 2005.]]
[27]
G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. AEGIS: architecture for tamper-evident and tamper-resistant processing. In the 17th International Conference on Supercomputing, pages 160--171, 2003.]]
[28]
G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Efficient memory integrity verification and encryption for secure processors. In the 36th International Symposium on Microarchitecture, pages 339--350, 2003.]]
[29]
C. Wang. A security architecture for survivability mechanism. PhD thesis, University of Virginia, October 2000.]]
[30]
J. Yang, Y. Zhang, and L. Gao. Fast Secure Processor for Inhibiting Software Piracy and Tampering. In the 36th International Symposium on Microarchitecture, pages 351--360, 2003.]]
[31]
Y. Zhang, L. Gao, J. Yang, X. Zhang, and R. Gupta. SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In The 11th International Symposium on High-Performance Computer Architecture, pages 352--362, 2005.]]
[32]
X. Zhuang, T. Zhang, H.-H. S. Lee, and S. Pande. Hardware Assisted Control Flow Obfuscation for Embedded Processors. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 292--302, 2004.]]
[33]
X. Zhuang, T. Zhang, and S. Pande. HIDE: An Infrastructure for Efficiently Protecting Information Leakage on the Address Bus. In the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 72--84, 2004.]]

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cover image ACM Conferences
PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques
September 2006
308 pages
ISBN:159593264X
DOI:10.1145/1152154
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 September 2006

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  1. address bus leakage protection
  2. secure processor

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  • (2017)ObfusMemProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080230(107-119)Online publication date: 24-Jun-2017
  • (2014)Memory encryptionACM Computing Surveys10.1145/256667346:4(1-26)Online publication date: 1-Mar-2014
  • (2013)Design space exploration and optimization of path oblivious RAM in secure processorsACM SIGARCH Computer Architecture News10.1145/2508148.248597141:3(571-582)Online publication date: 23-Jun-2013
  • (2013)Design space exploration and optimization of path oblivious RAM in secure processorsProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485971(571-582)Online publication date: 23-Jun-2013
  • (2011)Architectural Support for Enhancing Critical Secrets Protection in Chip-MultiprocessorsPervasive Information Security and Privacy Developments10.4018/978-1-61692-000-5.ch012(172-183)Online publication date: 2011
  • (2009)Making secure processors OS- and performance-friendlyACM Transactions on Architecture and Code Optimization10.1145/1498690.14986915:4(1-35)Online publication date: 23-Mar-2009
  • (2007)Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)10.1109/MICRO.2007.16(183-196)Online publication date: Dec-2007
  • (2006)Authentication Control Point and Its Implications For Secure Processor DesignProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.11(103-112)Online publication date: 9-Dec-2006

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