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Testing implementations of transactional memory

Published: 16 September 2006 Publication History

Abstract

Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software. Given the subtle issues involved with concurrency and atomicity, however, it is important that transactional memory systems be carefully designed and aggressively tested to ensure their correctness. In this paper, we propose an axiomatic framework to model the formal specification of a realistic transactional memory system which may contain a mix of transactional and non-transactional operations. Using this framework and extensions to analysis algorithms originally developed for checking traditional memory consistency, we show that the widely practiced pseudo-random testing methodology can be effectively applied to transactional memory systems. Our testing methodology was successful in finding previously unknown bugs in the implementation of TCC, a transactional memory system. We study two flavors of the underlying analysis algorithm, one incomplete and the other complete, and show that the complete algorithm while being theoretically intractable is very efficient in practice.

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cover image ACM Conferences
PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques
September 2006
308 pages
ISBN:159593264X
DOI:10.1145/1152154
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 September 2006

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Author Tags

  1. specification
  2. testing
  3. transactional memory
  4. verification

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Cited By

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  • (2020)Formalizing determinacy of concurrent revisionsProceedings of the 9th ACM SIGPLAN International Conference on Certified Programs and Proofs10.1145/3372885.3373820(258-269)Online publication date: 20-Jan-2020
  • (2019)Transaction Protocol Verification with Labeled Synchronization LogicNASA Formal Methods10.1007/978-3-030-20652-9_19(280-297)Online publication date: 28-May-2019
  • (2018)The semantics of transactions and weak memory in x86, Power, ARM, and C++ACM SIGPLAN Notices10.1145/3296979.319237353:4(211-225)Online publication date: 11-Jun-2018
  • (2018)The semantics of transactions and weak memory in x86, Power, ARM, and C++Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192373(211-225)Online publication date: 11-Jun-2018
  • (2018)CheckMateProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00081(947-960)Online publication date: 20-Oct-2018
  • (2017)A Transactional Correctness Tool for Abstract Data TypesACM Transactions on Architecture and Code Optimization10.1145/314896414:4(1-24)Online publication date: 14-Nov-2017
  • (2017)Automated Synthesis of Comprehensive Memory Model Litmus Test SuitesACM SIGARCH Computer Architecture News10.1145/3093337.303772345:1(661-675)Online publication date: 4-Apr-2017
  • (2017)Automated Synthesis of Comprehensive Memory Model Litmus Test SuitesACM SIGPLAN Notices10.1145/3093336.303772352:4(661-675)Online publication date: 4-Apr-2017
  • (2017)Automated Synthesis of Comprehensive Memory Model Litmus Test SuitesACM SIGOPS Operating Systems Review10.1145/3093315.303772351:2(661-675)Online publication date: 4-Apr-2017
  • (2017)Automated Synthesis of Comprehensive Memory Model Litmus Test SuitesProceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3037697.3037723(661-675)Online publication date: 4-Apr-2017
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